Design Engineer - Physical Design at Cadence Design Systems

Shanghai, Shanghai, China -

Full Time

Start Date

Immediate

Expiry Date

02 Jul, 26

Salary

0.0

Posted On

03 Apr, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Design, Floorplan, CTS, STA, Physical Verification, Power Analysis, Perl, C Shell, TCL, Makefile, Python, Innovus, ICC, Calibre, Tempus, PrimeTime

Industry

Software Development

Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. About the team: Our team deliver many high-performance products based on the industry’s most advanced technology with high frequencies up to 8800MHz.Our product processes include TSMC 2nm/3nm/5nm/7nm/12nm and Samsung 2nm/4nm/5nm/7nm/8nm/10nm, etc. In the team you will face great challenges such as FP, CTS, STA, etc. At the same time, you will get rich experience and advanced methodology. Job Responsibilities: Focus on high-speed digital DDR PHY IP physical implementation, develop necessary scripts or tools to enhance current PD design flow. Work in product projects, including but not limited to: complete the project tasks; solve design issue and provide flow to check and avoid similar issue; analyze and summarize PPA optimization methodologies and results, implement optimal design parameters and flows for different projects. Job Requirement: -BS with minimum 4 years of experience. MS with minimum 2 years of experience. -Good physical design experience in the digital implementation domain including Floorplan, CTS, STA, Physical verification, Power analysis. -Solid background in circuits, electronics, physics, be willing to learn new technology for cutting edge process node and advanced design methodology. -Skilled in scripting language, such as Perl, C shell, TCL, Makefile, Python. -Familiar with EDA tools like Innovus, ICC, Calibre, Tempus, PrimeTime, etc. We’re doing work that matters. Help us solve what others can’t. Additional Jobs Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. Read the policy(opens in a new tab) We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact staffing@cadence.com. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab). E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Responsibilities

Focus on high-speed digital DDR PHY IP physical implementation and develop scripts or tools to enhance the design flow. Analyze PPA optimization methodologies and implement optimal design parameters for various product projects.