Design Engineering Architect at Cadence Design Systems

Hämeenlinna, Kanta-Häme, Finland -

Full Time

Start Date

Immediate

Expiry Date

17 Apr, 26

Salary

0.0

Posted On

17 Jan, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Design Verification, Interconnects, NoCs, System Verilog, UVM, Programming Languages, Testbenches, Automated Flows, Regression Cycles, Scripting Languages, Interpersonal Skills, Team Management, Technical Contributions, Verification Plans, Code Review, Technical Debt

Industry

Software Development

Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities Manage a team of verification engineers for interconnect IP. Also required to pitch in with the technical contributions as required. Relevant experience in interconnect and subsystems is strongly preferred Crafting and reviewing verification plan. Manage the overall execution on those plans to verify highly complex and configurable designs. Responsible for verification closure and sign off. Work closely with cross functional teams (DV/Arch/Design/PD/GUI). Identify and hire talent to grow the team as needed. Required Skills and Experience: 15+ years of design verification experience BS (or higher) in EE/Computer Engineering Experience in managing a team of 5+ engineers. Experience in hiring and building the team, training and developing engineers. Strong interpersonal skills. Excellent at identifying and communicating requirements, delegating tasks. Excellent knowledge of Interconnects, NoCs and design verification fundamentals. Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches. Strong technical skills to review the code, make constructive suggestions and overall ability to maintain the codebase to avoid future technical debt. Experience with development of fully automated flows, manage regression cycles and monitor coverage progression. Exposure to scripting languages like Perl, Unix shell or similar languages would be a plus. We’re doing work that matters. Help us solve what others can’t. Additional Jobs Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. Read the policy(opens in a new tab) We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact staffing@cadence.com. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab). E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Responsibilities

Manage a team of verification engineers for interconnect IP and contribute technically as needed. Oversee the execution of verification plans for complex designs and ensure verification closure.