Design for Test Engineer (m/f/d) - REF84987L at Aumovio

Regensburg, Bavaria, Germany -

Full Time

Start Date

Immediate

Expiry Date

15 Dec, 25

Salary

0.0

Posted On

16 Sep, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Electrical Engineering, Microelectronics, Physics, DFT Engineering, ATPG, JTAG, MBIST, SystemVerilog RTL, TCL, Python, Unix/Linux, DFT Tools, Communication Skills, Customer Focus, Motivation, Team Player

Industry

Motor Vehicle Manufacturing

Description

Company Description Since its spin-off in September 2025 AUMOVIO continues the business of the former Continental group sector Automotive as an independent company. The technology and electronics company offers a wide-ranging portfolio that makes mobility safe, exciting, connected, and autonomous. This includes sensor solutions, displays, braking and comfort systems as well as comprehensive expertise in software, architecture platforms, and assistance systems for software-defined vehicles. In the fiscal year 2024 the business areas, which now belong to AUMOVIO, generated sales of 19.6 billion Euro. The company is headquartered in Frankfurt, Germany and has about 87.000 employees in more than 100 locations worldwide. Job Description As DFT engineer (m/f/diverse) for Continental ASICs you define and implement DFT (Design for Test) and BIST (Built-In Self-Test) concepts, you also develop DFT specifications and driving DFT architecture and methods for designs as well as IPs to maximize test coverage while minimizing costs. You have the opportunity to work on Continental’s diverse innovative automotive applications and find optimized solutions for their specific needs. Special care must be taken to meet the stringent automotive requirements. Your tasks will focus on the following activities: Define and implement DFT (Design for Test) and BIST (Built-In Self-Test) concepts, as well as IPs to maximize test coverage while minimizing costs Define and develop scripts for automatic scan insertion, execute scan insertion and ATPG (Automatic Test Pattern Generation) Perform test coverage analysis and improvement Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans Develop full chip and block level DFT implementation from the Specifications and product coverage, quality, and manufacturability goals Collaboratively create DFT methodology innovations & enhancements for Continental Work in close cooperation with the two main interfaces chip design and semiconductor manufacturing as well as related areas Implement and verify testability features to our System-on-Chip designs Create and simulate test patterns for production testing Develop DFT specifications and drive flow and methodology enhancements Implement and validate DFT structures such as LBIST, MBIST, IP tests, Scan & compression etc. Give technical guidance to other DFT engineers, concept engineers, digital designers, physical implementation, and functional verification teams Verify, support and understanding of pattern delivery to the post-silicon test engineering teams. Delivering the full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester team’s needs Work with cross-functional IP and SOC teams to define strategy for DFT architecture, verification, and design flow automation Contribute throughout the whole development and give early feedback to the Concept, Architecture and Design Teams for possible issues for DFT Define, develop, improve DFT process flows and methodologies for continuous improvement Working closely with IC Design during test plan and DFT definition, pre-silicon verification (chip level verification) and post silicon validation Work closely with IP test development team, defining test schemes and implementation styles Qualifications Academic degree in Electrical Engineering/Microelectronics/Physics or comparable qualification Many years of relevant work experience Proven Expertise in DFT engineering, with a strong record of technical innovation Experience in developing DFT specifications and driving DFT architecture and methods for designs Experience in industrial standards and practices in DFT - including ATPG, JTAG, MBIST and trade-offs between test quality and test time Skilled in SystemVerilog RTL, TCL, Python, and Unix/Linux environments Familiarity with Siemens, Cadence, and Synopsys DFT tools Very good English language skills (both written and spoken) Team player with good communication and negotiation skills Customer focus (anticipates and understands the customers‘ needs) Motivation and inspiration (operates with integrity and demonstrates dynamism) Applications from severely handicapped people are welcome. Additional Information Ready to take your career to the next level? The future of mobility isn’t just anyone’s job. Make it yours! Join AUMOVIO. Own What’s Next.

Responsibilities

As a DFT engineer, you will define and implement DFT and BIST concepts, develop DFT specifications, and drive DFT architecture to maximize test coverage while minimizing costs. You will also lead SOC Design for Test efforts and collaborate with chip design and semiconductor manufacturing teams.