PREFERRED EXPERIENCE:

• Extensive hardware verification experience.
• Must be proficient in Verilog, System Verilog, UVM, and working in Linux and Windows environments.
• Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation tools.
• Must have excellent programming skills.
• Must have exposure to Makefile and other scripting languages like Perl, Python and Ruby

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_

THE ROLE:

The CIT team is a dynamic and innovative team dedicated to pushing the boundaries of hardware development. We are seeking skilled and motivated verification engineers to join our growing team and to contribute to the success of cutting-edge IPs. We are currently looking for an experienced ASIC Design Verification engineer who will be involved in all aspects of design verification activities, using the latest methodologies with the help of automation, keeping power and performance in mind. The candidate will utilize/develop a variety of verification components, using the latest verification methodologies to achieve an excellent RTL/Firmware design quality.
The CIT team designs AMD chiplet technology. The Design Verification group within this team is responsible for developing a scalable DV flow with new emphasis on automation, power, and performance. The NBIO organization has great diversity of talent across the globe. Our management fosters and encourages continuous technical innovation to showcase successes and to facilitate continuous career development.

KEY RESPONSIBILITIES:

• Closely work with architects and designers to develop verification strategies and execution plans.
• Participate in the verification of complex IP blocks, take end to end ownership of key features for all projects.
• Work on test plans, test case development, testbench enhancement, regression, and coverage closure.
• Deploying industry-leading verification methodologies, such as UVM and Formal Verification.
• Developing testbenches and verification components such as UVCs, models, BFMs, and re-usable verification environments.
• Writing, modifying, and maintaining constraint-random and directed test cases and libraries in System Verilog/UVM.
• Analyzing functional, code, and test plan coverage.
• Implementing assertions, checkers, and monitors.
• Triaging and debugging regressions.
• Reproducing functional bugs found in silicon, in simulation and/or Formal Verification tools.
• Conducting and participating in code reviews.