Design Verification Engineer at Advanced Micro Devices, Inc

Vancouver, British Columbia, Canada -

Full Time

Start Date

Immediate

Expiry Date

20 May, 26

Salary

0.0

Posted On

19 Feb, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

UVM, System Verilog, Test Plans, Testbenches, Verification Components, BFMs, Verification Environments, Directed Test Cases, Random Test Cases, Assertions, Checkers, Monitors, EDA Tools, Design Verification, Debugging Regressions, Code Reviews

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. DESIGN VERIFICATION ENGINEER THE ROLE: AMD is looking for motivated individuals seeking opportunities to solve complex problems in a fast-paced work environment. The successful candidate will be involved in all aspects of AMD's next generation products. This includes verifying PCI Express designs using latest UVM standard and develop comprehensive test plan to ensure coverage closure. The position allows exposure to all aspect of ASIC design stages. THE PERSON: Creative innovator and thinker who loves technical problems and detail-oriented tasks Exhibits relentless commitment to help the team meet quality and development goals on schedule Drives to learn and perform at his or her highest potential in a technical capacity Thrives in both a team environment and in individual contribution Communicates openly and clearly in meetings, presentations, emails, and reports Able to learn independently and acquire new skills required for the job Flexible in working hours to accommodate working with co-workers in different time-zones KEY RESPONSIBILITIES: Writing/Implementing/Reviewing Test Plans Developing Testbenches and Verification Components such as UVCs, models, BFMs, and Re-usable Verification Environments Writing, Modifying, and Maintaining Random and Directed Test Cases and Libraries in System Verilog/UVM Analyzing Functional, Code, and Test Plan Coverage Implementing Assertions, Checkers, and Monitors Utilizing In-House and 3rd Party IP/SOC CAD and EDA Tools for Design Verification Deploying Industry-Leading Verification Methodologies such as UVM Triaging and Debugging Regressions Reproducing Functional Bugs found in Silicon in Simulation Verification tools Conducting and participating in Code Reviews Technical leadership is an asset, including driving projects from start to the finish and design verification sign-off PREFERRED EXPERIENCE: Testbench Architecture, System Verilog, UVM Digital Design in RTL, Verilog HDL C/C++, Java, or other object-oriented programming language Perl, Ruby, Shell-scripting, UNIX/LINUX Environment VCS, NCSIM, Questa, or other simulator and associated waveform viewers such as Verdi PC System Architecture: PCI Express, x86, ARM On-Chip Bus Interfaces and Architectures: AMBA AXI, OCP, PIPE ACADEMIC CREDENTIALS: Masters or Bachelor degree with working experience in ASIC area LOCATION: Vancouver, British Columbia #LI-DD3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

Key responsibilities involve writing, implementing, and reviewing test plans, developing testbenches and verification components using UVM standards, and writing/maintaining test cases in System Verilog/UVM. The role also includes analyzing coverage, implementing assertions, utilizing EDA tools, and debugging regressions found in silicon.