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Design Verification Engineer at Apple
, , Israel -
Full Time

Start Date

Immediate

Expiry Date

10 Mar, 26

Salary

0.0

Posted On

10 Dec, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

SoC Verification, SoC Architecture, Verification Flows, Dynamic Methods, Coverage-Based Methods, Formal Methods, System Verilog, UVM, Verification Infrastructure Development, Scripting, Programming, Perl, Python, C, C++, TCL

Industry

Computers and Electronics Manufacturing

Description
In this visible role, you will be responsible for defining DV methodologies, test-bench infrastructure, and for project execution for the next generation Apple high-speed interfaces to enable groundbreaking I/O connectivity solutions for Apple product lines. You will have regular interaction with Architecture, Design and SW teams, and the opportunity to influence our future products. The people who work here have reinvented entire industries with all Apple hardware products. The same passion for innovation that goes into our products also applies to our practices - strengthening our dedication to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple products. DESCRIPTION You will develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors. Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market. You will work closely with the design team to ensure timely delivery of quality designs. Working with methods to accelerate verification time. Involvement in Post-Silicon Validation. MINIMUM QUALIFICATIONS +6 years of experience in SoC Verification You will need to have advanced knowledge of SoC architecture/design, in-depth knowledge of verification flows, and a broad system view Expected to have a deep understanding and shown experience in advanced verification processes, including dynamic, coverage-based, and formal methods Extensive experience with System Verilog or UVM Experience with verification infrastructure development Scripting and programming experience using several of the following: Perl, Python, Verilog, SystemVerilog, C, C++, and TCL – an advantage PREFERRED QUALIFICATIONS B.Sc / M.Sc in Electrical or Computer Engineering
Responsibilities
You will develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors. You will work closely with the design team to ensure timely delivery of quality designs.