Design Verification Engineer at Apple

San Diego, California, United States -

Full Time

Start Date

Immediate

Expiry Date

22 Jan, 26

Salary

0.0

Posted On

24 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Design Verification, UVM, System Verilog, System C, C/C++, Python, Test Planning, Problem Solving, Coverage Driven Verification, Constraint Random Testing, SVA, DV Methodologies, ML Tools, Debug Methodologies, Cellular Protocols, ASIC Design

Industry

Computers and Electronics Manufacturing

Description

Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something — you’ll add something. Do you have a passion for innovation and technical excellence? Do you thrive on solving complex problems that push the boundaries of what's possible? Join our team to verify innovative, high-throughput cellular baseband modems and transceiver link controllers that power communication for millions of users worldwide. DESCRIPTION As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems. Working on innovative baseband modems and RF link controllers for Apple's SOCs, you'll craft highly reusable UVM verification environments that set the standard for quality and efficiency. You'll develop comprehensive coverage-driven and directed test cases that thoroughly validate complex IP and subsystem designs, working closely with multi-functional teams throughout the process. In this role, you'll drive methodology innovation by deploying sophisticated tools and techniques that elevate verification practices and ensure tape-out readiness. Collaborating with product development teams across Apple, you'll help deliver cellular systems that redefine industry capabilities and enhance customer experiences globally. This position offers exceptional opportunities to deepen your expertise across cellular protocols, complex IP and subsystem architectures, advanced fabric protocols, and sophisticated debug methodologies. You'll gain experience with best-in-class design verification practices, co-verification techniques with models and firmware, and industry-standard low-power architectures. We're looking for engineers with hands-on ASIC design verification experience using reusable verification methodologies such as UVM. The ideal candidate excels at detailed test planning, adapts optimally to evolving requirements, knowledge of the latest ML based tools to improve productivity and is driven to achieve the highest quality standards. You thrive in collaborative environments and are eager to address the verification challenges inherent in complex, high-performance cellular systems. If you want to contribute to products that impact customers worldwide while advancing your technical expertise, we'd love to hear from you. MINIMUM QUALIFICATIONS BS and a minimum of 10 years relevant industry experience. Strong knowledge of System Verilog and UVM. Skilled in System C, C/C++, Python/perl. Highly proficient in developing and establishing DV Methodologies. Highly proficient in developing workflows using ML tools. Experience developing System Verilog Testbench with UVM methodology from scratch. Experience with constraint random testing, SVA, Coverage driven verification. Strong test planning and problem-solving skills. PREFERRED QUALIFICATIONS Master of Science degree in Electrical Engineering/Computer Science. Experience in C/C++ modeling for design verification. Knowledge of 4G/5G cellular physical layer operation (3GPP). Experience with verification of embedded processor cores. Hands-on verification experience of Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.

Responsibilities

As a Design Verification Engineer, you'll ensure the quality and reliability of next-generation cellular systems by crafting reusable UVM verification environments. You'll develop comprehensive test cases and collaborate with multi-functional teams to drive methodology innovation.