Design Verification Engineer for Cellular SoC (m/f/d) at Apple

Linz, Upper Austria, Austria -

Full Time

Start Date

Immediate

Expiry Date

18 Jan, 26

Salary

0.0

Posted On

20 Oct, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Design Verification, Cellular SoC, HW Design, SW Design, UVM, RF Modems, Test Benches, Collaboration, Quality Assurance, Bug Detection, Communication Skills, RISC-V Architecture, Assertion-Based Verification, System Integration, Hands-On Verification, Verification Languages

Industry

Computers and Electronics Manufacturing

Description

Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job, and there's no telling what you could accomplish. Hard-working people and inspiring, innovative technologies are the norms here. Enter a multifunctional role as a Design Verification Engineer in our team in Linz, Austria. We are at the center of the IP and full-chip verification effort within a silicon design group responsible for verifying the state-of-the-art Cellular RF SoCs. This position requires someone comfortable with diving into HW design and verification engineering. DESCRIPTION You will need a fundamental understanding of HW and SW design, as well as the eagerness to do hands-on verification. The cool thing is, once you crack the design verification world, it will potentiate your knowledge of HW/SW systems in the RF world. We will introduce you to assertion-based verification, simulation acceleration, and formal methods. You will learn special verification languages as universal verification methodology (UVM) or formal description languages, like SVA, flanked by AI-based approaches. Our team is a very strong cellular hardware design verification team with very good individual communication. You will work in a strong team setup with a lot of interpersonal interaction that will help you to get a very wide understanding of our work, as well as the sub-system and system integration into RF modems. You will build metric-driven verification plans from specifications, review them, and refine them to achieve coverage targets. You will define functional verification requirements based on design requirements and architect and develop UVM-based, highly reusable test benches starting from different components over a cluster into SoC levels. MINIMUM QUALIFICATIONS Proven experience in taping out SoC systems with embedded processor cores and hands-on verification experience in UVM environments. Strong collaborative work experience with system, design, and firmware teams. Verification and Validation approach, as well as outstanding sense and dedication to the quality of deliverables A detective skill for finding bugs and weaknesses Having a good view of the definition and design process of a chip Holistically thinking beyond the design verification domain boundaries Good interpersonal and communication skills English language proficiency is required for this position PREFERRED QUALIFICATIONS Bachelor's or Master's (or higher degree) in Electrical Engineering or Communication Engineering with extensive years of working experience. System know-how in the cellular RF transceiver domain is a plus Proficiency in RISC-V architecture, encompassing design, verification, and programming, is highly valued Knowledge of assertion-based verification would be nice to have Ideally, you worked on system/IP definition, system/IP validation, system/IP design, system/IP testing, or similar Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.

Responsibilities

As a Design Verification Engineer, you will be responsible for verifying Cellular RF SoCs and developing metric-driven verification plans. You will work closely with a strong team to define functional verification requirements and architect reusable test benches.