POSITION OVERVIEW:

We are seeking an experienced Design Verification Engineer to join our team in Austin, TX. The ideal candidate will have deep expertise in SystemVerilog/UVM-based verification and Design-for-Testability (DFx) methodologies including Scan, BIST, JTAG, and ATPG. This role requires hands-on skills in verifying complex SoCs and IP blocks, ensuring DFx features are functionally correct, and collaborating across pre-silicon and post-silicon teams.

REQUIRED SKILLS & EXPERIENCE:

• 7+ years of experience in ASIC/SoC design verification.
• Strong proficiency in SystemVerilog and UVM methodologies.
• Hands-on experience with DFx verification (Scan, BIST, JTAG, ATPG).
• Proficiency in debugging at RTL and gate-level using simulation tools.
• Solid understanding of DFT methodologies and test coverage analysis.
• Experience with EDA tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
• Familiarity with SVA (SystemVerilog Assertions) and coverage metrics.
• Excellent problem-solving skills and ability to work in a fast-paced, cross-functional team environment.

PREFERRED QUALIFICATIONS:

• Knowledge of low-power design and verification (UPF/CPF).
• Familiarity with silicon bring-up and post-silicon validation.
• Experience working on high-performance SoCs or processor subsystems.
• Strong scripting skills (Python, Perl, TCL, or Shell) for verification automation.
  Job Type: Contract
  Pay: From $55.00 per hour
  Work Location: In perso

• Develop, implement, and maintain test plans, testbenches, and verification environments using SystemVerilog and UVM.
• Verify DFx features (Scan, BIST, JTAG, ATPG) for complex SoC designs.
• Perform coverage analysis and closure to ensure robust verification.
• Debug complex design and verification issues, working closely with design and validation teams.
• Use industry-standard EDA tools (Synopsys, Cadence, Mentor) for simulation, waveform analysis, and coverage reporting.
• Drive pre-silicon verification and collaborate with post-silicon validation teams to ensure functional bring-up success.
• Create and maintain verification documentation including test specifications, results, and sign-off reports.
• Work with cross-functional teams (design, DFT, validation, architecture) to ensure first-pass silicon success.