Design Verification Engineer at Meta

, , -

Full Time

Start Date

Immediate

Expiry Date

05 Feb, 26

Salary

0.0

Posted On

08 Nov, 25

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Design Verification, SystemVerilog, UVM, C/C++, EDA Tools, Scripting, Revision Control, Verification Infrastructure, ARM, RISC-V, CPU, GPU, Assertions, Formal, Emulation, ASIC Development

Industry

Software Development

Description

Reality Labs focuses on delivering Meta's vision through AI-first devices that leverage our wearable technologies. The compute performance and power efficiency requirements require custom silicon. We are driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable Meta’s Wearable devices that blend our real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. Responsibilities Define and implement verification plans, and build test benches for block, IP, sub-system, and SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality Debug, root-cause and resolve functional failures in the design, partnering with the Design team Qualifications Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta 2+ years of hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience with revision control systems like Mercurial(Hg), Git or SVN Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch Experience verifying ARM/RISC-V based sub-systems and SoCs Experience verifying CPU/GPU designs Experience in one or more of the following areas: SystemVerilog Assertions (SVA), Formal, and Emulation Track record of 'first-pass success' in Application-Specific Integrated Circuit (ASIC) development cycle

Responsibilities

Define and implement verification plans, and build test benches for various levels of verification. Collaborate with cross-functional teams to ensure the highest design quality and debug functional failures.