Design Verification Engineer, Staff

at  Synopsys

WE ARE:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

• Developing and executing verification test plans and test cases for SoC devices.
• Creating and maintaining verification environments using UVM methodology.
• Collaborating with design and architecture teams to understand specifications and define verification scope.
• Debugging and resolving issues creatively and efficiently during the verification process.
• Participating in code reviews and providing feedback to improve overall design quality.
• Mentoring and guiding junior verification engineers on best practices and methodologies.