Design Verification Engineer, Staff at Synopsys
Zapopan, Jal., Mexico -
Full Time


Start Date

Immediate

Expiry Date

30 Apr, 25

Salary

0.0

Posted On

01 Feb, 25

Experience

0 year(s) or above

Remote Job

No

Telecommute

No

Sponsor Visa

No

Skills

Good communication skills

Industry

Information Technology/IT

Description

WE ARE:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

Responsibilities
  • Developing and executing verification test plans and test cases for SoC devices.
  • Creating and maintaining verification environments using UVM methodology.
  • Collaborating with design and architecture teams to understand specifications and define verification scope.
  • Debugging and resolving issues creatively and efficiently during the verification process.
  • Participating in code reviews and providing feedback to improve overall design quality.
  • Mentoring and guiding junior verification engineers on best practices and methodologies.
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