REQUIRED EXPERIENCE:

• Expertise in SystemVerilog, UVM/OVM, Perl, C/C++, and formal tools like Jasper.
• Deep protocol knowledge: CXL 2.0, PCIe Gen5, MACSec, Ethernet, TCP/IP, Fibre Channel.
• Experience with tools: VCS, NC-Sim, ModelSim, Debussy, Synplicity.

PREFERRED EXPERIENCE

• Experience with FPGA platforms and Quartus software.
• Familiarity with SoC integration flows and automated testbench generation.
• Strong customer engagement and communication skills.
• Passion for building high-performing teams and fostering innovation.

QUALIFICATIONS:

• M.S. in Computer Engineering or related field preferred (B.S. required).
• 20+ years in ASIC/FPGA design verification, with 10+ years in technical leadership.

ABOUT THE ROLE:

Intel’s Customer Engineering Center of Excellence is seeking a highly experienced Design Verification Director to lead verification efforts across a portfolio of Intel products. This role is critical to delivering high-quality silicon for a variety of applications. The ideal candidate will bring deep technical expertise in pre-silicon verification, IP development, and engineering leadership, with a proven track record of managing large DV teams and delivering production-grade IPs.

RESPONSIBILITIES:

• Lead DV strategy and execution for Ips.
• Architect scalable UVM/OVM-based testbenches across block, IP, and subsystem levels.
• Drive formal verification using Jasper and coverage-driven constraint random methodologies.
• Manage and mentor DV teams (10–20+ engineers), setting quality metrics and ensuring zero bug escapes.
• Collaborate cross-functionally with architecture, design, software, and customer teams to ensure robust IP delivery.
• Oversee quarterly IP releases and customer handoffs, including Tier-1 OEM engagements and defense sector deployments.
• Enable automation and reuse in verification environments to support continuous integration and SoC scalability.

WORK MODEL FOR THIS ROLE

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.