Design Verification Lead
at Apple
Cupertino, California, USA -
Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
---|---|---|---|---|---|---|---|
Immediate | 16 Feb, 2025 | USD 293800 Annual | 18 Nov, 2024 | 10 year(s) or above | Design,Assertions,Team Spirit,Gls,Communication Skills,Formal Verification | No | No |
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Description:
SUMMARY
Posted: Nov 14, 2024
Role Number:200578830
Are you a leader and want to apply your engineering background to make big things happen, and can you influence, connect, get results and communicate effectively while delivering on a predictable and dynamic schedule? The Custom Silicon Management Group provides critical custom silicon for all mobile products including iPhone, iPad, iPod, and AppleTV. We have an extraordinary opportunity for senior level engineers to drive and lead technical engagements between Apple and silicon suppliers working on groundbreaking technologies! We are looking for a remarkable Design Verification Lead to work with multi-functional teams and external vendors to define, develop and productize the next generation of mobile solutions.
DESCRIPTION
As a CSM (Custom Silicon Management) DV lead, you will be leading the DV front for vendor silicons (power, display, touch and sensors, accessories). You will manage throughout the entire project phase, from specification, planning, execution, to sign-off. Key tasks include - Work closely with internal & external teams to review specifications, improve DV plans & methodologies, and ensure full verification coverage. - Collaborate with design & micro-architecture teams to understand the functional & performance goals of the design. - Lead and track DV progress and quality. Review DV architecture, implementation, metrics. Provide technical guidance to planning, execution, and long term technology roadmap.
- BS degree and 10 years of industry experience.
- Experience with modern verification languages, including SystemVerilog / UVM .
PREFERRED QUALIFICATIONS
- Advanced knowledge of ASIC architecture, design, and verification flow.
- Expert knowledge of state-of-the-art verification flow and methodology, such as constrained random, functional/code coverage, assertions, GLS.
- Knowledge of Formal verification, low power verification and analog mixed signal simulation are a plus.
- Excellent social and communication skills, team spirit, and the passion to take on diverse challenges.
- Knowledge of industry standard interfaces.
Responsibilities:
- BS degree and 10 years of industry experience.
- Experience with modern verification languages, including SystemVerilog / UVM
REQUIREMENT SUMMARY
Min:10.0Max:15.0 year(s)
Information Technology/IT
IT Software - Other
Information Technology
BSc
Proficient
1
Cupertino, CA, USA