Design Verification Manager(DV) at Avicena Tech

Sunnyvale, California, United States -

Full Time

Start Date

Immediate

Expiry Date

02 Jan, 26

Salary

0.0

Posted On

04 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Design Verification, Team Leadership, Verification Strategy, Methodology Ownership, Testbench Development, Resource Management, Cross-Functional Collaboration, Quality Assurance, Tool Management, Technical Oversight, System Verilog, UVM, Communication Skills, High-Speed Interfaces, Formal Verification, Scripting

Industry

Description

About the role: Avicena is seeking an experienced and strategic Manager of Design Verification (DV) to lead our team in ensuring the functional excellence of our next-generation silicon photonics and optical interconnect chips. You will be responsible for defining the verification strategy, managing team execution, and driving best-in-class methodologies to achieve first-pass silicon success on complex, high-speed digital integrated circuits (ICs). Responsibilities: Team Leadership & Management: Lead, mentor, and manage a team of Design Verification Engineers. Responsibilities include hiring, performance reviews, career development, and resource allocation. Verification Strategy: Define and own the overall DV strategy and execution plan for multiple complex digital blocks and full-chip verification, ensuring alignment with architectural goals and tape-out schedules. Methodology Ownership: Drive the adoption, maintenance, and continuous improvement of cutting-edge verification methodologies (primarily UVM) and flows to enhance efficiency, reusability, and quality across projects. Testbench Development: Develop comprehensive and reusable verification environments (Testbenches) using advanced methodologies like UVM (Universal Verification Methodology). Resource and Schedule Management: Establish project schedules, track progress, manage verification resources, and proactively identify and mitigate technical and schedule risks. Cross-Functional Collaboration: Serve as the primary point of contact for verification, liaising extensively with Architecture, Frontend Design, Physical Design, and Firmware teams to ensure clear communication and seamless hand-offs. Quality and Coverage Sign-off: Define and enforce rigorous sign-off criteria for all functional, code, and formal coverage metrics, ensuring the designs are fully verified and meet tape-out quality standards. Tool and EDA Management: Evaluate, select, and manage relationships with EDA vendors for simulation, formal, and debug tools, ensuring the team has the necessary resources. Technical Oversight: Provide high-level technical guidance and oversight on complex verification challenges, debug efforts, and the application of advanced techniques (e.g., formal verification). Qualifications: Required: Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience: 8+ years of total industry experience in ASIC/SoC design verification, including 2+ years of experience in a formal management or technical lead role with direct reports. Methodology Expertise: Deep, hands-on expertise in defining and deploying comprehensive, scalable verification environments using System Verilog and UVM. Project Execution: Proven track record of successfully driving the verification of at least two complex, high-speed ASIC designs from planning through to tape-out and silicon validation. System Understanding: Strong system-level understanding and ability to translate high-level specifications into effective verification goals. Communication Skills: Exceptional communication, negotiation, and presentation skills to effectively manage team dynamics and influence cross-functional decisions. Preferred (Nice to Have): Experience in verifying high-speed interfaces (e.g., SerDes, PCIe, Ethernet) or optical communication protocols. Exposure to forward error correction (FEC), scrambling, and other digital data communication techniques. Direct experience with formal verification techniques and tool integration into the standard flow. Proficiency in advanced scripting/automation (Python) for large-scale data analysis and flow management. Experience with low-power verification strategies and tools.

Responsibilities

Lead and manage a team of Design Verification Engineers to ensure the functional excellence of silicon photonics and optical interconnect chips. Define the verification strategy and drive best-in-class methodologies to achieve first-pass silicon success on complex digital integrated circuits.