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Developer ASIC at Ericsson
Stockholm, , Sweden -
Full Time

Start Date

Immediate

Expiry Date

21 Jan, 26

Salary

0.0

Posted On

23 Oct, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

RTL Design, Microarchitecture, Verilog, SystemVerilog, Functional Verification, UVM, Test Plans, Assertions, Coverage Models, Logic Synthesis, Timing Closure, Chip-Level Architecture, Low-Power Design Techniques, DFT Methods, Scripting Languages, Communication Skills

Industry

Telecommunications

Description
Expertise in RTL design and microarchitecture using Verilog/SystemVerilog, including FSMs, pipelines, and clocking. Good understanding of functional verification methodologies, including SystemVerilog and UVM. Good ability to collaborate with verification teams to develop test plans, assertions, and coverage models. Experience with simulators such as VCS, Questa, and ModelSim for thorough verification and debugging. Proficiency in logic synthesis (Synopsys Design Compiler, Cadence Genus) and timing closure with PrimeTime. Experience defining chip-level architecture, including block diagrams, AXI/PCIe/Ethernet protocols, memory hierarchies, and DMA engines. Knowledge of low-power design techniques (UPF/CPF), DFT methods (scan chains, MBIST), and PPA trade-offs. Skilled in scripting languages (Python, Tcl, Perl) for design automation and system-level modeling. Excellent communication skills, with leadership in cross-functional teams and mentoring junior engineers ​What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like. We encourage you to consider applying to jobs where you might not meet all the criteria. We recognize that we all have transferrable skills, and we can support you with the skills that you need to develop. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. learn more. Primary country and city: Sweden ; Stockholm
Responsibilities
The developer will focus on RTL design and microarchitecture, collaborating with verification teams to develop test plans and assertions. They will also define chip-level architecture and ensure timing closure.