Developer ASIC at Ericsson

Stockholm, , Sweden -

Full Time

Start Date

Immediate

Expiry Date

07 Apr, 26

Salary

0.0

Posted On

07 Jan, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Design, Microarchitecture, Verilog, SystemVerilog, Functional Verification, UVM, Simulators, Logic Synthesis, Timing Closure, Chip-Level Architecture, Low-Power Design Techniques, DFT Methods, Scripting Languages, Communication Skills, Mentoring, Collaboration

Industry

Telecommunications

Description

Join our Team About this opportunity: Are you driven by innovation and ready to influence the next generation of high-performance ASICs? We are seeking a Senior ASIC Design Engineer who combines deep technical mastery with a strategic, big-picture mindset. This is a role for someone who thrives in designing for today while envisioning tomorrow—someone who sees technology not just as circuits, but as platforms for future growth. You will be part of a collaborative, forward-looking team where your expertise will guide both current projects and the architectural direction of upcoming designs. We’re scaling for the future—this is your chance to leave a legacy at Ericsson that truly lasts. What You Will Do • Architect and implement advanced ASIC IP and subsystems enabling next-generation wireless solutions. • Own RTL design and verification at block and subsystem levels, driving quality from concept through tape-out. • Collaborate closely with verification, physical design, and system teams to ensure robust integration and performance. • Document architectures, define design specifications, and propose enhancements for scalability and sustainability. • Lead process improvements and champion automation to increase design efficiency. • Mentor engineers and foster a culture of knowledge sharing and technical excellence. Skills You Bring • Expertise in RTL design and microarchitecture using Verilog/SystemVerilog, including FSMs, pipelines, and clocking. • Good understanding of functional verification methodologies, including SystemVerilog and UVM. • Good ability to collaborate with verification teams to develop test plans, assertions, and coverage models. • Experience with simulators such as VCS, Questa, and ModelSim for thorough verification and debugging. • Proficiency in logic synthesis (Synopsys Design Compiler, Cadence Genus) and timing closure with PrimeTime. • Experience defining chip-level architecture, including block diagrams, AXI/PCIe/Ethernet protocols, memory hierarchies, and DMA engines. • Knowledge of low-power design techniques (UPF/CPF), DFT methods (scan chains, MBIST), and PPA trade-offs. • Skilled in scripting languages (Python, Tcl, Perl) for design automation and system-level modeling. • Excellent communication skills, with leadership in cross-functional teams and mentoring junior engineers What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like. We encourage you to consider applying to jobs where you might not meet all the criteria. We recognize that we all have transferrable skills, and we can support you with the skills that you need to develop. Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more. Primary country and city: Sweden ; Stockholm Job Stage: 7

Responsibilities

You will architect and implement advanced ASIC IP and subsystems for next-generation wireless solutions. Additionally, you will collaborate with various teams to ensure robust integration and performance.