• Develop DFT specifications and concepts based on DFT requirements
• Architect top- and block-level DFT solutions for SoCs with multiple hierarchical partitions and Mixed-Signal IPs with complex DFT and ultra-low power requirements
• Implement DFT solutions on top- and block level for large-scale SoC designs, including Scan-Compression, OCC, LBIST, Core Wrapping, MBIST, MBISR, IJTAG and Boundary Scan
• Analyze and solve testability issues
• Generate and simulate test patterns
• Write and verify test mode timing constraints
• Collaborate with the physical design team to address timing violations, signal/power integrity concerns and so on.
• Work with test engineers to bring up test patterns on silicon and debug yield problems or failing patterns
• Be a main driver for continuous improvements of our in-house DFT flow and methodology
• Technical lead of DFT engineers within projects
• Mentor and guide junior engineers

REQUIREMENTS:

• Bachelor’s/Master’s Degree in Electrical Engineering, Information Technology or similar
• 10+ years experience as DFT engineer
• Strong knowledge of state-of-the-art DFT techniques and concepts like
• Scan test including Compression, On-chip clock controllers, IEEE 1500 core wrapping, LBIST
• JTAG, Boundary Scan, iJTAG, AC coupled JTAG
• MBIST including Built-in self-repair
• Experience to plan, drive and implement DFT insertion and validation for SoCs from concept to post-silicon bring up
• Deep experience with industry standard DFT tools from Synopsys, Siemens or Cadence for test insertion, pattern generation and verification
• Strong experience in gate-level simulation with and w/o SDF
• Experience in developing and improving DFT flows for industry standard DFT tools
• Experience in Synthesis and STA
• Very good programming skills in TCL

GOOD TO HAVE SKILLS:

• Working knowledge of hardware description languages (VHDL or Verilog and SystemVerilog)
• Experience or working knowledge of SERDES, Analog /mixed-signal DFT techniques (like IOBIST, loop-backs etc.)
• Experience in Post Silicon Pattern conversion for Testers, Pattern Bring-up & Debug, Silicon Characterization etc.
• Experience with DFT for advanced memory technologies like MRAM
• Experience with UPF and power-aware simulations
• Experience with DFT for functional safety applications, ISO26262
• Experience or familiarity in back-end chip design, Timing Closure, CDC flows

ABOUT US:

Racyics® is Europe’s leading design service provider for mixed-signal system-on-chip design and turnkey services in advanced nodes.
We deliver professional analog, digital and mixed-signal design services tailored to the customers’ needs with focus on realization of complex System-on-Chips in leading edge technology nodes. Our team of more than 100 employees covers the complete chip design process up to system architecture development. Racyics is working for major German and international semi-custom companies both as a service provider and in collaborative partnerships.
Working at Racyics comes with many benefits, including flexible working hours, mobile work, a financial contribution to your childcare costs and great team events.

Please refer the Job description for details