DFT Design Engineer at Intel - Dubai

, Arizona, United States -

Full Time

Start Date

Immediate

Expiry Date

20 Jun, 26

Salary

149150.0

Posted On

22 Mar, 26

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Design For Test, RTL Coding, SCAN, MBIST, BSCAN, TAP, Timing Closure, ATPG, TCL, Python, Perl, C++, GLS, SoC Integration, Functional IP Blocks, Automatic Test Equipment

Industry

Semiconductor Manufacturing

Description

Job Details: Job Description: Perfect Opportunity for Career Growth: This role is ideally suited for recent graduates and early-career professionals passionate about building expertise in Design for Test (DFT). No previous DFT experience is required – we're seeking motivated individuals with a genuine interest in evolving their careers in this specialized field. The Role and Impact: As a DFT Design Engineer, you will play a vital role in shaping the quality and performance of Intel's silicon products. You will contribute to the development of cutting-edge technologies by designing and verifying robust Design for Test (DFT) features that ensure manufacturability and reliability. Your work will directly impact Intel's ability to deliver high-quality products to market quickly, meeting both performance and quality objectives. This position offers the opportunity to collaborate with cross-functional teams, influence design methodologies, and drive innovation in test strategies for SoC and functional IP blocks. Key Responsibilities: Develop logic design, register transfer level (RTL) coding, and implement DFT architectures including SCAN, MBIST, BSCAN, and TAP. Collaborate in the definition of architecture and microarchitecture features for DFT blocks and subsystems. Optimize logic to achieve power, performance, area, timing, test coverage, and defect per million (DPM) goals. Write and generate RTL and structural code for DFT integration, ensuring design integrity for physical implementation. Review and execute verification plans to ensure design features meet architecture specifications. Resolve RTL test failures and implement corrective measures to ensure feature correctness. Support SoC customers for successful integration of DFT blocks, contributing to high-quality IP and SoC designs. Develop high-volume manufacturing (HVM) test content for rapid bring-up and production deployment on automatic test equipment (ATE). Collaborate with post-silicon and manufacturing teams to verify features in silicon and support debugging requirements. Qualifications: Minimum Qualifications: Bachelor's degree in Computer or Electrical Engineering, or a related field with no prior experience required. Interest in DFT as a career This position is based in Fort Collins, Colorado and requires on-site presence 4 days per week at our office location. Preferred Qualifications: Familiarity with test architecture including SCAN, MBIST, BSCAN, and TAP. Familiarity with RTL coding, DFT techniques, and timing closure methods. Experience with design tools and methodologies such as ATPG and coverage analysis. Experience configuring EDT setups and resolving stuck-at and at-speed test scenarios. Proficient programming skills in TCL, Python, Perl, and/or C++. Knowledge of GLS for test scenario resolution and ATPG coverage analysis. Strong communication and collaboration skills, with a focus on teamwork across diverse engineering groups. Join us in advancing Intel's legacy as a technology leader. Apply today to be a part of our journey in innovating the future of silicon design and manufacturing. Job Type: College Grad Shift: Shift 1 (United States of America) Primary Location: Virtual US Additional Locations: Business group: At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 03/31/2026 * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology. Benefits Internships Life at Intel Locations Recruitment Process Discover your place in our world-changing work.

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Responsibilities

The engineer will develop logic design, RTL coding, and implement DFT architectures such as SCAN, MBIST, BSCAN, and TAP, while optimizing logic for power, performance, area, timing, and test coverage goals. Key duties also involve writing RTL code for DFT integration, reviewing verification plans, resolving test failures, and developing high-volume manufacturing test content.