DFT Engineer at Advanced Micro Devices, Inc

, , China -

Full Time

Start Date

Immediate

Expiry Date

28 Jun, 26

Salary

0.0

Posted On

30 Mar, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

DFT Scan Insertion, ATPG, Pattern Generation, Simulation, Coverage Analysis, ATE Test Support, Scan Quality Improvement, Automation Script Development, Processor Architecture, Digital Design, Verification, Communication, Problem-Solving, DFD, DRC

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: You are responsible to RTG SOC DFT scan domain related work, tile/top level scan insertion/ATPG/Pattern generation/simulation/coverage analyze and ATE test support. You are also responsible to co-work with other teams to make sure our scan quality and improve our coverage. You should contribute to the development of automation environment to improve work efficiency. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: In this role, the candidate will be responsible for： Work with cross team to finish tile scan insertion and ATPG in each milestone; Complete tile level pattern generation and simulation/debug Complete tile level coverage analysis and improve the test coverage Setup chip level ATPG environment and finish chip level DRC and simulation Generate production scan pattern and guarantee the pattern quality Take part in DFD(design for debug) related work and do support for function team Develop automation script to improve the work efficiency. PREFERRED EXPERIENCE: Strong knowledge of DFT domain; Solid experience with DFT scan insertion and ATPG; Familiar with ASIC/DFT regular tools, DC tool/Tessent tool/VCS tool; Fully experience with ATE Bring up ACADEMIC CREDENTIALS: Bachelor or MS or PHD in Electrical Engineering, Computer Engineering or Computer Science; BS 6+ years or MS 3+ years or PhD 1+ years’ experience in DFT; LOCATION: B49, Zhangdong Road 1387, Shanghai #LI-VC1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The engineer will be responsible for RTG SOC DFT scan domain tasks, including tile/top level scan insertion, ATPG, pattern generation, simulation, coverage analysis, and ATE test support. This role also requires collaboration with other teams to ensure scan quality and contributing to automation development to enhance work efficiency.