DFT Engineer at Advanced Micro Devices, Inc

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

06 Aug, 26

Salary

0.0

Posted On

08 May, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

DFT ATPG, Digital Design, Scan Pattern Generation, Scan Chain Trace, Scan DRC Analysis, Silicon Bring-up, Mentor Graphics, Synopsys Tetramax, VCS, Verdi, FSDB, Static Timing Analysis, Timing Closure, Scripting, Computer Architecture, Functional Verification

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. MTS SILICON DESIGN ENGINEER THE ROLE: As a MTS Silicon Design Engineer, you will work with DFT experts and DFT Architects, drive and execute DFT ATPG for the various Cores of AMD. THE PERSON: You have a passion for modern, complex processor architecture, digital design, verification in general and Design For Testability (DFT) in particular. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Drive DFT ATPG for the IPs of various Cores of AMD. Coordinate with DFT RTL engineers to generate and verify Scan Patterns for the various Cores IPs. Write ATPG scripts, understand ATPG tools, do Scan Chain trace, analyze Scan DRCs, generate Scan Patterns and Verify/Simulate the Scan Patterns and achieve the targeted Scan Coverage for the IP/design. Responsible for DFT quality metrics like DRC cleanliness, first time right Scan Patterns and ATPG coverage. Work on Silicon bring-up of Scan Patterns with Product Engineering and SoC DFT teams. PREFERRED EXPERIENCE: Project level experience with Digital Design concepts and hands-on DFT ATPG knowledge. Extensive experience and working knowledge of DFT ATPG tools like Mentor Graphics (Siemens), Synopsys Tetramax and/or functional verification tools like VCS, Verdi, FSDB. Exposure to DFT Architecture and Design. Good understanding of computer organization/architecture. Exposure to Static Timing Analysis (STA), Timing Closure and DFT Timing is required. Excellent hands-on debug skills and scripting skills are essential. Must have good communication skills and the ability to interact and work with global teams. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electronics Engineering/Electrical Engineering with atleast 7+ years of DFT ATPG experience. #LI-AA1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

Drive and execute DFT ATPG for various AMD core IPs, including generating and verifying scan patterns. Responsible for maintaining DFT quality metrics and collaborating with product engineering for silicon bring-up.