DFT Engineer at Advanced Micro Devices, Inc

, , China -

Full Time

Start Date

Immediate

Expiry Date

09 Sep, 26

Salary

0.0

Posted On

11 Jun, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC DFT Design, DFT Verification, Scan, Boundary Scan, MBIST, Analog Macro Test Logic, Timing Constraints, Timing Closure, ATE Bring-up, DFX, Microprocessor Design, Problem Solving, English Communication

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The GE S3 DFT team fully own AMD S3BU (Strategic Silicon Solution Business Unit) SOC DFT definition, Implementation, verification till final silicon bring up. You will directly work on cutting edge DFT technology and address the challenge of AMD leading SOC suffering. Also, you will participants all the development, discussion around world, including NA, India, and China. THE PERSON: Hands on working experience on ASIC DFT design and verification Familiar with entire ASIC design flow Experience with microprocessor design a big plus Should have strong problem-solving skills KEY RESPONSIBILITIES: Qualified candidate will perform some or all functions below: Participate in SOC full Chip DFT feature and architecture definition Responsible for DFT specification generation and review Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic. Perform verification on all DFT structures Generate DFT related timing constraints and work with PD team for timing closure Generate and verify DFT structural patterns and functional patterns Participate in ATE bring-up and debug the DFT patterns on ATE Design and implement other DFX (debug, characterization, yield etc) logics PREFERRED EXPERIENCE: Good English hearing, speaking, reading, and writing capabilities Good communication skills ACADEMIC CREDENTIALS: BS in EE & CS. MS preferred, with 3+ years’ experience LOCATION: Shanghai, Beijing #LI-VC1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The role involves defining, implementing, and verifying SOC DFT architecture, including SCAN, MBIST, and Boundary SCAN. Responsibilities also include generating timing constraints, verifying structural patterns, and performing ATE bring-up and debug.