DFT Engineer at NVIDIA

Yokneam Ilit, Haifa District, Israel -

Full Time

Start Date

Immediate

Expiry Date

25 Jul, 26

Salary

0.0

Posted On

26 Apr, 26

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

DFT, ATPG, Scan Insertion, ASIC Design, TCL, Perl, Python, Unix Shell Scripts, BIST, On-chip Scan Compression, Fault Models, Fault Simulation, DC, Fusion, Genus, Hardware Technology

Industry

Computer Hardware Manufacturing

Description

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the SCAN INSERTION team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing. Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements! What you’ll be doing: You will be in charge of state of the art Design for Test (SCAN INSERTION) flows and implementation Take full SCAN INSERTION ownership end to end on a project, from Arch & planning to implementation and verification Inventing and maintaining automation flows that provide SCAN INSERTION implementation to project What we need to see: 0-2 years of hands on DFT/ATPG/SCAN experience knowledge & technical experience in DFT ASIC Design and in ATPG/SCAN tools (DC/Fusion/Genus) Strong programming skills in scripting languages BSc. in Electrical Engineering or Computer engineering Quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility Ways to stand out from the crowd: Knowledge of DFT including SCAN INSERTION, BIST, on-chip scan compression, fault models, ATPG, and fault simulation Experience in Synopsis/Mentor SCAN tools Programming languages: TCL, Perl, Phyton & Unix shell scripts NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you're creative and autonomous, we want to hear from you! You will have the opportunity to work on some of the most incredible products on the market today. NVIDIA pioneered accelerated computing. Today, our AI infrastructure powers global intelligence, transforming every industry. Learn more about NVIDIA.

Responsibilities

You will be responsible for end-to-end Design-for-Test (SCAN INSERTION) flows, including architecture, planning, implementation, and verification. Additionally, you will invent and maintain automation flows to support SCAN INSERTION implementation across various projects.