DFT Engineer at NVIDIA

Hyderabad, Andhra Pradesh, India -

Full Time

Start Date

Immediate

Expiry Date

25 Apr, 26

Salary

0.0

Posted On

25 Jan, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Design For Testability, Static Timing Analysis, ECO, ASIC Design Flow, HDL, Digital Logic Design, RTL Verification, Gates Verification, Simulation, BIST Architecture, JTAG, IEEE1149.1, IEEE1500, Scan ATPG, Compression Techniques, Memory Test, Scripting Languages

Industry

Computer Hardware Manufacturing

Description

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. What you'll be doing: As a member in our team, you will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, memory BIST and scan compression. Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features. In addition, you will help develop and deploy DFT methodologies for our next generation products. Be apart of innovation to strive improve the quality of DFT methods. You will also need to work with multi-functional teams to incorporate DFT features into the chip. Occasional travel and also some late hours online meetings involved during critical milestones. What we need to see: BSEE or MSEE from reputed institutions or equivalent experience. 2+ Years of experience preferably in Design for testability (DFT) You should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design. Experience in RTL and Gates verification and simulation. You need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500. Strong DFT knowledge in Scan ATPG, compression techniques and memory test. Strong analytical and problem solving skills. Expert coding skills in industry standard scripting languages. Extraordinary written and oral communication skills with the curiosity to work on rare challenges. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people on the planet working for us. If you're creative and autonomous, we want to hear from you! NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. #LI-Hybrid NVIDIA is the world leader in accelerated computing. NVIDIA pioneered accelerated computing to tackle challenges no one else can solve. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society. Learn more about NVIDIA.

Responsibilities

You will be responsible for the design and implementation of test access mechanisms, memory BIST, and scan compression. Additionally, you will verify and bring up silicon for Scan ATPG and other DFT features.