DFT Hardware Test Engineer/ Architect– JTAG, ICT & Functional Test at Advanced Micro Devices, Inc

Austin, Texas, United States -

Full Time

Start Date

Immediate

Expiry Date

16 Sep, 26

Salary

0.0

Posted On

18 Jun, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

DFT Principles, JTAG Boundary Scan, ICT Development, Functional Test Fixtures, Python, Perl, Root Cause Analysis, Test Coverage Analysis, PCB Manufacturing, Analog Circuit Testing, Digital Circuit Testing, Mixed-Signal Circuit Testing, XJTAG, Corelis, Teradyne, Keysight

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for a DFT Hardware Test Engineer/ Architect– JTAG, ICT & Functional Test who thrives in a collaborative environment and plays a key role in ensuring our products meet the highest standards of quality and reliability. In this role, you’ll partner closely with design, manufacturing, and quality teams to shape how our boards are validated, influence decisions that improve product robustness, and help streamline how we bring complex hardware to market. You’ll contribute to an environment that values curiosity, clear communication, and continuous improvement—making a direct impact on how efficiently and confidently we deliver products to customers. THE PERSON: A clear, collaborative communicator who partners effectively across teams. They bring strong analytical thinking, disciplined problem solving, and calm, methodical troubleshooting under pressure. Highly organized and detail‑oriented, they document and present findings succinctly, manage priorities well, and drive issues to resolution. They adapt quickly, embrace continuous improvement, and build trust through reliability, integrity, and a quality‑focused mindset. KEY RESPONSIBILITIES: Collaborate with hardware design teams to integrate DFT features early and ensure board‑level testability. Develop and maintain Functional Test fixtures and Tests. Develop, debug, and optimize JTAG boundary scan test programs (e.g., XJTAG, Corelis, ASSET InterTech) for interconnect, memory, and device programming. Troubleshoot and root‑cause boundary scan test failures. Develop and maintain ICT programs on platforms such as Teradyne and Keysight, including fixture design and optimization. Generate ICT test programs for analog, digital, and mixed‑signal circuits, and troubleshoot ICT failures. Work with manufacturing teams to refine ICT processes and improve yields. Analyze test coverage metrics, identify improvement areas, and implement strategies to increase coverage and reduce escapes. Partner with design and manufacturing to resolve testability issues. Create and maintain test documentation including test plans, procedures, and reports; present results and track key metrics (coverage, yield, failure rates). Stay current on test technologies, drive process improvements, and participate in continuous improvement initiatives. PREFERRED EXPERIENCE: Deep understanding of DFT principles, boundary‑scan methodologies, and ICT development. Hands‑on experience with JTAG tools (e.g., XJTAG, Corelis, ASSET InterTech) and ICT platforms (e.g., Teradyne, Keysight). Demonstrated ability to analyze and improve test coverage and troubleshoot complex board‑level failures. Proficiency in scripting (Python, Perl) to automate test flows and enhance efficiency. Familiarity with IPC standards, PCB manufacturing practices, and failure‑analysis techniques. Comfortable working cross‑functionally in fast‑paced engineering environments, driving quality and testability improvements. ACADEMIC CREDENTIALS Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field is preferred. This role is not eligible for visa sponsorship. #LI-BM1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The role involves integrating DFT features into hardware designs and developing JTAG and ICT test programs to ensure board-level testability. The engineer will collaborate with manufacturing and design teams to optimize yields and resolve complex hardware failures.