Start Date
Immediate
Expiry Date
21 Sep, 26
Salary
0.0
Posted On
23 Jun, 26
Experience
10 year(s) or above
Remote Job
Yes
Telecommute
Yes
Sponsor Visa
No
Skills
Verilog RTL Design, VLSI Digital Design, People Management, ASIC/FPGA Design Flows, System Verilog, UVM, CDC/RDC Techniques, Python, Perl, TCL, Shell Scripting, Micro-architecture Specification, Hardware Verification, RTL Synthesis, Timing Sign-off, Project Planning
Industry
Software Development