We are hiring a Digital Design Engineer to contribute to our edge and FPGA development product line. This role focuses on RTL development and simulation using industry-standard tools. You will be joining a team that values technical rigor, ownership, and collaboration across disciplines.

REQUIREMENTS

• 3+ years of experience with both VHDL and Verilog
• 3+ years of experience with Python
• 5+ years of experience with RTL simulation and debugging using any of the following: Cadence Xcelium, Synopsys VCS, Xilinx xsim
• Comfortable working in Linux and command-line environments

• Design and implement digital logic using VHDL and Verilog
• Perform RTL simulation and debugging using tools such as: Cadence Xcelium, Synopsys VCS, Xilinx xsim
• Write Python scripts for test automation, simulation workflows, or tooling
• Work within a Linux command-line development environment