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What will you do at Ciena as a Digital Design Engineer – Digital Synchronization?

The Wavelogic family of products are widely used in Ciena’s optical fiber transmission solutions, and are one of the main contributors to Ciena’s success in the telecommunications industry. To further strengthen our team, we are looking for an enthusiastic digital design engineer who will be involved in the design of these products, working within a team of digital design engineers, verification engineers and architects. Your role as a digital design engineer will focus on digital synchronization and digital PLL development, in which you will propose innovative solutions, in order to design power and area optimized timing and synchronization related functional blocks and algorithms for the Wavelogic family of products.

• You are expected to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects
• You will focus on the digital PLL development, jitter, wander and synchronization functions and will define algorithms to extract and propagate source timing and rate information form standard client protocols across the digital optical network.
• You will produce an implementation specification document and have it reviewed by your team, architects and analog/board designers if applicable
• You are accountable for the creation and integration of new and existing RTL and/or C source code, algorithms and functions
• You are responsible for designer testing of your code as well as debugging of your code during simulation, regression and formal verification
• You will assist the verification team in determining coverage and provide design assertions and waivers as needed
• You are held responsible for crafting timing constraints for your code, and will participate in synthesis log reviews, constraint reviews, timing report analysis, layout and backend reviews
• You will be involved in lab validation of the product and its prototype
• You are expected to report on status updates on a regular basis

What technical experience and personal skills are required for this role?

• Electrical or computer engineering or other applicable scientific degree at the BEng/BSc or MEng/MSc level
• Knowledge and experience with system timing and synchronization algorithms, digital PLL design for timing extraction, rate matching, protocol mapping (e.g. GMP, BMP)
• Knowledge and experience with digital filter design, Matlab modeling
• A highly motivated self-starter, able to work independently, while being a great teammate
• Ability to methodically solve complex technical problems
• Excellent organization, written and oral (English) communication skills
• Proficiency above the intermediate level with use of System Verilog for design
• Familiarity with digital (including formal) verification methods
• Experience with digital design synthesis, STA, timing closure and asynchronous clock crossing
• Good understanding of timing/power/area analysis and trade-offs

What additional assets can help me in this role?

• Experience with digital ASIC design backend process
• Experience with digital design for low power
• Experience with standards and protocols such as OTN, B100G, Ethernet, GMP mapping
• Experience with using Jira for bug tracking and GIT for source code management and revision tracking
• Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++, System C

The above lists are intended to describe the general nature and level of work, and they are not intended to be a comprehensive list of all responsibilities, duties and skills required to be qualified and to be performed by the selected candidate. You will have an opportunity to better understand the role through the interview experience.
Pay Range: The annual salary range for this position is $100,900 - $161,100.
Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.
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At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require

The Wavelogic family of products are widely used in Ciena’s optical fiber transmission solutions, and are one of the main contributors to Ciena’s success in the telecommunications industry. To further strengthen our team, we are looking for an enthusiastic digital design engineer who will be involved in the design of these products, working within a team of digital design engineers, verification engineers and architects. Your role as a digital design engineer will focus on digital synchronization and digital PLL development, in which you will propose innovative solutions, in order to design power and area optimized timing and synchronization related functional blocks and algorithms for the Wavelogic family of products.

• You are expected to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects
• You will focus on the digital PLL development, jitter, wander and synchronization functions and will define algorithms to extract and propagate source timing and rate information form standard client protocols across the digital optical network.
• You will produce an implementation specification document and have it reviewed by your team, architects and analog/board designers if applicable
• You are accountable for the creation and integration of new and existing RTL and/or C source code, algorithms and functions
• You are responsible for designer testing of your code as well as debugging of your code during simulation, regression and formal verification
• You will assist the verification team in determining coverage and provide design assertions and waivers as needed
• You are held responsible for crafting timing constraints for your code, and will participate in synthesis log reviews, constraint reviews, timing report analysis, layout and backend reviews
• You will be involved in lab validation of the product and its prototype
• You are expected to report on status updates on a regular basi

What technical experience and personal skills are required for this role?

• Electrical or computer engineering or other applicable scientific degree at the BEng/BSc or MEng/MSc level
• Knowledge and experience with system timing and synchronization algorithms, digital PLL design for timing extraction, rate matching, protocol mapping (e.g. GMP, BMP)
• Knowledge and experience with digital filter design, Matlab modeling
• A highly motivated self-starter, able to work independently, while being a great teammate
• Ability to methodically solve complex technical problems
• Excellent organization, written and oral (English) communication skills
• Proficiency above the intermediate level with use of System Verilog for design
• Familiarity with digital (including formal) verification methods
• Experience with digital design synthesis, STA, timing closure and asynchronous clock crossing
• Good understanding of timing/power/area analysis and trade-off

What additional assets can help me in this role?

• Experience with digital ASIC design backend process
• Experience with digital design for low power
• Experience with standards and protocols such as OTN, B100G, Ethernet, GMP mapping
• Experience with using Jira for bug tracking and GIT for source code management and revision tracking
• Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++, System