WHY WE ARE HIRING

We’re looking for an IP Verification and System Validation Engineer to join our Security team and be part of realizing a whole new paradigm in semiconductors and microprocessor design. The role is wide and varied and involves the verification of digital IP blocks and internal validation of their functionality as part of an application-specific platform. The first project you will be involved with is an EU-funded project called Listen2Future, where we are tasked with developing a secure platform on FPGA that includes many IP blocks developed in-house. The project is focused on developing and using high-bandwidth MEMS microphones for various applications including medical monitoring and predictive maintenance within critical national infrastructure.
Our Security team is a mixed team with expert architecture, design, hardware, software, and testing capabilities. We sit within the Codasip Labs department, which is the innovation hub of Codasip. We evaluate new technology that shows commercial potential and evolve that technology to the point where it can be made into a product. As part of this journey, we design IP and build FPGA platforms in order to create proof-of-concepts and technology demonstrators. Where appropriate, we take the selected IP further to become an ASIC-quality product.

The role demands flexibility, determination, and lateral thinking.

• Department: Labs
• Employment: Full-time
• Experience level: Mid-Senior
• Location of work is Munich, Germany
• Please note this role is only open to candidates with working rights in Germany

THE FOLLOWING SKILLS AND EXPERIENCE ARE NICE TO HAVE:

• Technical background in FPGA system prototyping and debug
• Embedded software development in C/C++
• Experience with software automation
• Familiarity with common lab equipment (oscilloscopes, protocol analyzers, etc.)
• Knowledge of RISC-V

WHAT WILL YOU DO?

• Verify IP blocks using standard SystemVerilog UVM test benches
• System-level validation of application-specific FPGA platforms
• Testing the whole FPGA platform before release to customers or other partners in the project.

THE FOLLOWING SKILLS ARE ESSENTIAL TO PERFORM THE JOB DUTIES:

• Experience with hardware verification (VHDL/Verilog simulation, formal or UVM)
• Knowledge of HDL languages (Verilog, VHDL, or SystemVerilog)
• Active usage of versioning tools (Git -preferred)
• Ability to test and debug complete systems running on an FPGA platform
• Familiarity with Xilinx/AMD FPGA platforms, Vivado, and simulation tools like QuestaSim or Verilator
• Excellent English communication skills. English. Our team is highly distributed, so English is the primary language

The role demands flexibility, determination, and lateral thinking.

• Department: Labs
• Employment: Full-time
• Experience level: Mid-Senior
• Location of work is Munich, Germany
• Please note this role is only open to candidates with working rights in German