Digital IC Design Engineer (EP-ESE-ME-2025-225-GRAP) at CERN

Geneva, Geneva, Switzerland -

Full Time

Start Date

Immediate

Expiry Date

29 Jun, 26

Salary

7004.0

Posted On

31 Mar, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Design, Verilog, SystemVerilog, VHDL, Python, TCL, Shell, Git, UVM, ASIC Design, VLSI Principles, Digital Simulation, Timing Closure, Place & Route, DRC, LVS

Industry

Research Services

Description

Job Description We are looking for a digital ASIC design engineer to work on the next generation of advanced MAPS particle-detector ASICs for the CERN detector complex. You will contribute to the design, implementation, and verification of high-performance digital readout and control circuits that meet demanding targets in speed, density, power efficiency, and radiation tolerance, while collaborating closely with analog and verification specialists. Your responsibilities: Conceive and optimise system-level architectures and data processing strategies. Design, synthesise, and implement RTL, including timing closure and place & route of complex designs. Contribute to chip signoff through physical design checks (DRC, LVS, ERC) and power integrity analysis. Participate in formal verification using UVM methodologies. Manage the full RTL-to-GDS flow and physical signoff with professional EDA tools. Collaborate and communicate effectively within a multidisciplinary team. Learn and share knowledge, solve problems, and achieve results through teamwork. Your profile: Experience in digital IC design with a strong understanding of VLSI principles. Experience in the design and implementation of digital or mixed-signal circuits in ASICs or FPGAs. Additionally, experience with digital simulation techniques and tools would be an advantage. Skills: Proficiency in RTL design using hardware description languages (Verilog/SystemVerilog, VHDL). Proficiency in scripting languages (Python, TCL, Shell) and versioning tools (Git). Additionally, experience with functional verification methodologies (UVM/SystemVerilog) and simulation tools would be an advantage. Spoken and written English, with a commitment to learn French. Eligibility criteria: You have a professional background in Electronics engineering (or a related field) and have either: a Master's degree with 2 to 6 years of post-graduation professional experience; or a PhD with no more than 3 years of post-graduation professional experience. You have never had a CERN fellow or graduate contract before. Additional Information Job closing date: 21.04.2026 at 23:59 CEST. Contract duration: 24 months, with a possible extension up to 36 months maximum. Job flexibility: Hybrid Target start date: 1 June 2026 This position involves: Work during nights, Sundays and official holidays, when required by the needs of the Organization. Job reference: EP-ESE-ME-2025-225-GRAP Field of work: Electrical or Electronics Engineering Benchmark job: 200050 - Electronics Engineer Global Benefits A monthly stipend between 6372-7004 Swiss Francs per month (tax free) depending on your degree. 30 days of paid leave per year plus 2 weeks annual closure. Coverage by CERN’s comprehensive health insurance scheme (for yourself, your spouse and children), and membership of the CERN Pension Fund. Family, child and infant monthly allowances depending on your individual circumstances. A relocation package (installation grant and travel expenses) depending on your individual circumstances. Possibility to extend your contract up to 36 months. On-the-job and formal training including language classes. Overview of CERN - Discover a world where the impossible is made possible! At CERN, the European Organization for Nuclear Research, we are pushing the frontiers of science and technology. Our groundbreaking work brings together not only physicists but also a diverse range of professionals from engineering, technical, scientific, and administrative fields. Together, we foster an environment where innovation and collaboration thrive. Every day, we face exciting new challenges and opportunities to contribute to cutting-edge research that shapes our understanding of the universe. We meet these challenges through the diverse perspectives within our teams, ensuring every contribution is valued and driving our shared sense of inclusion and purpose. Diversity is a core value of CERN since its foundation, and it remains central to our mission and continued success. If you are ready to be part of a dynamic, inclusive community pushing the boundaries of knowledge, CERN is the place where your curiosity and skills can thrive. Be part of our mission to uncover what lies at the heart of the universe! TAKE PART! More information about us, here: careers.cern

Responsibilities

The role involves designing, implementing, and verifying high-performance digital readout and control circuits for advanced particle-detector ASICs, requiring conception and optimization of system-level architectures and data processing strategies. Responsibilities include managing the full RTL-to-GDS flow, performing physical design checks, and participating in formal verification using UVM methodologies.