Digital Senior SerDes Design Engineer at Ciena Limited

Brunswick, Lower Saxony, Germany -

Full Time

Start Date

Immediate

Expiry Date

18 Sep, 26

Salary

174000.0

Posted On

20 Jun, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

System Verilog, Digital Design, RTL Coding, Static Timing Analysis (STA), Timing Closure, Asynchronous Clock Crossing, Synthesis, Power Analysis, Area Analysis, DSP Design, Python, C/C++, Git, Jira, Verification Methods, SerDes Design

Industry

Telecommunications

Description

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. What will you do at Ciena as a Senior Digital Design Engineer? The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions and are one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for an enthusiastic digital design engineer who will be involved in the design of these products, working within a team of digital design engineers, verification engineers and architects. Your role as a senior digital design engineer will be to propose innovative solutions, in order to design power and area optimized functional blocks for the Wavelogic family of products. As a senior digital design engineer, you are expected to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects You will produce an implementation specification document and have it reviewed by your team, architects, analog designers if applicable You are accountable for the creation and integration of new and existing RTL and/or C source code, algorithms and functions You are held responsible for designer testing of your code as well as debugging of your code during simulation and regression verification You will assist the verification team in determining coverage and provide design assertions and waivers as needed You are held responsible for crafting timing constraints for your code, and will participate in synthesis log reviews, constraint reviews, timing report analysis, layout and backend reviews You will be involved in lab validation of the product and its prototype if applicable You are expected to report on status updates on a regular basis What technical experience and personal skills are required for this role? Electrical or computer engineering, or other applicable scientific degree at the BEng/BSc or MEng/MSc level Proficiency above the intermediate level with use of System Verilog for design A highly motivated self-starter, able to work independently, while being a team player Ability to methodically solve complex technical problems Excellent organization, written and oral (English) communication skills Familiarity with digital (including formal) verification methods Experience with digital design synthesis, STA, timing closure and asynchronous clock crossing Good understanding of timing/power/area analysis and trade-offs What additional assets can help me in this role? Experience with digital silicon design backend process Experience with digital design for low power Experience with DSP design Knowledge of industry standards such as IEEE, Ethernet, or OIF standards for optical communication Experience with using GIT for source code management and revision tracking Experience with using Jira for schedule planning, assignment tracking and bug reporting Familiarity with programming languages such as Python, Make, bash, object-oriented programming, C, C++, System C The annual pay range for this position in Ottawa is $109,000 - $174,000 CAD. Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available. Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require. Create an account to sign up for job alerts and be notified about new opportunities, customized for you. Dig deeper into who we are, what we do, and what you can expect as a member of our team. Meet the people who are shaping the future of communication and explore the culture we’ve built together at CienaLife.

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Responsibilities

Design power and area optimized functional blocks for the Wavelogic family of products using RTL and C source code. Collaborate with architects and systems engineers to implement specifications and perform lab validation of prototypes.