As a Digital Synthesis Engineer, you will be involved in:• Developing and running synthesis flows for complex digital designs and IP• Preparing and managing synthesis constraints for block and top level designs• Analysing timing, area and power results and identifying opportunities for optimisation• Working closely with RTL designers to resolve synthesis and implementation challenges• Supporting design integration and ensuring blocks are suitable for downstream implementation• Investigating critical paths and helping improve overall design performance• Supporting physical design activities and resolving issues between front end and back end teams• Contributing to improvements across synthesis methodologies, flows and development processes• Working with engineers across the ASIC development lifecycle to support successful silicon delivery

• The ideal candidate will have:• Experience in digital ASIC, SoC or IC development• Strong experience with synthesis and digital implementation flows• Good understanding of RTL and Verilog/SystemVerilog• Experience working with timing constraints and analysing synthesis results• Understanding of timing, power and area optimisation• Familiarity with ASIC development methodologies and the wider RTL to silicon flow• Experience working in a Linux or Unix environment• Good scripting or programming skills would be beneficial