Digital Team Lead/Sr Team Lead at Silvaco

Cairo, Cairo, Egypt -

Full Time

Start Date

Immediate

Expiry Date

12 Aug, 26

Salary

0.0

Posted On

14 May, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Verilog RTL Design, ASIC/FPGA Design Flow, System Verilog, UVM, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Python Scripting, Perl Scripting, Shell Scripting, RTL Synthesis, Timing Sign-off, Micro-architecture Specification, Hardware Verification, Functional Coverage, Code Coverage, High Level Synthesis

Industry

Software Development

Description

Company Description Are you ready for exciting development opportunities with massive growth potential? Do you thrive in a fast-paced environment, embrace large responsibilities, and dream of working on cutting-edge technologies with a super bright team? As a leading provider of high-performance mixed-signal IPs integrated into many of today's most exciting applications, such as smart phones, automotives, IoT, wearables, and sensors, among many others. We seek the brightest minds to work hands-on with cutting-edge technologies alongside our world-class engineers. Job Description Responsible for micro-architecture specification and RTL design of modules in Verilog Responsible for project direction and planning, mentoring and technical guidance of the team. Lead development teams in the development of digital controllers through the full project lifecycle, including analysis, design, development, verification, testing and implementation. Leading verification team to develop advanced test plans. Hardware verification of the digital module using cutting edge FPGA kits. Provide technical leadership on one or more projects Solve complex problems which may be multidisciplinary or require an in-depth analysis of variable factors Defining project-specific best practices, and lead code reviews. Identifying opportunities for improving productivity and reducing errors. Communication of project status, risk and successes to internal and external stakeholders. Team planning and team member resource utilization. Qualifications Essential Qualifications and Experience: Bachelor’s degree of: Electronics Engineering. Years of experience in the same field: +7 Years of experience in VLSI Digital Design/Verification Strong knowledge of Verilog RTL design/simulation. Proficiency in ASIC/FPGA design flows including RTL Synthesis, Place and Route, and Timing Sign-off. Strong knowledge of clock domain crossing (CDC) and reset domain crossing (RDC) techniques Solid understanding of System Verilog, UVM, RTL/gate verification techniques Solid understanding of functional and code coverage metrics and closure Strong knowledge in shell/perl/python scripting languages. Desirable Qualifications and Experience: Knowledge of high level synthesis techniques and C-simulation/validation Masters Degree is a plus. Additional Information Life at Mixel At Mixel, a Silvaco company, we believe in empowering our people and meeting them where they are in their careers. Our Total Rewards package is designed to reflect the local culture and community where our employees live and work — because we know success starts with feeling valued and supported. Our people are our greatest strength. We also believe in a pay-for-performance philosophy — rewarding impact, recognizing achievements, and providing security for the future. Here are some of the key highlights: · Competitive pay · Annual and spot bonuses · Long-term incentive plan awards (RSUs) · Health benefits · Paid holidays and time off · Various learning and leadership opportunities

Responsibilities

Lead the development of digital controllers through the full project lifecycle, from micro-architecture specification to implementation. Provide technical guidance, mentor the team, and manage project planning and stakeholder communication.