Digital Verification Development Engineer at Silvaco

Cairo, Cairo, Egypt -

Full Time

Start Date

Immediate

Expiry Date

12 Aug, 26

Salary

0.0

Posted On

14 May, 26

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

SystemVerilog, UVM, Verilog, Object-Oriented Programming, Functional Coverage, Code Coverage, Unix/Linux, RTL Design, Synthesis, CDC Analysis, Shell Scripting, Perl, TCL, FPGA Prototyping, Verification IP, Gate Level Simulation

Industry

Software Development

Description

Company Description Mixel, a Silvaco Company, is an innovator of high-performance analog mixed signal semiconductor IPs whose solutions are powering Mobile, Display, Camera, Automotive, VR, AR and AI applications. Our mission is to provide our customers and partners with outstanding mixed-signal, silicon-proven IPs, creating in the process a differentiating technology that sets your products apart. At Mixel, you will find an inspiring environment with a strong focus on technical innovation, people well-being, no layers of management, and the freedom to make meaningful contributions in a setting that encourages creative thinking. We value open communication, empathy, mutual trust, and respect. Job Description Develop test plan from specification and architect system level verification environments. Develop and maintain UVM-based testbenches for block-level and subsystem-level verification Write constrained-random stimulus, scoreboards, monitors, and coverage models in SystemVerilog Contribute to regression infrastructure, continuous integration flows, and internal verification methodology Drive functional and code coverage closure; analyze coverage holes and add targeted tests Integrate and configure VIP (Verification IP) for standard protocols Support FPGA-based prototyping and pre-silicon bring-up with validation test suites Execute RTL/Gate level simulations and analyze results. Contribute to design/verification process automation. Qualifications Essential Qualifications and Experience: Bachelor’s degree of: Electronics/Computer Engineering. Years of experience in the same field: 0-3 Years of experience in developing SV-based verification environments. Strong knowledge of Verilog, System Verilog, and object-oriented programming languages. Strong proficiency in UVM methodology Solid understanding of functional and code coverage metrics and closure English Language Proficiency: Fluency Computer skills required: Unix/Linux operating system. Desirable Qualifications and Experience: Familiarity with RTL design, synthesis, and CDC analysis. Working knowledge of shell, Perl, and TCL scripting. Additional Information Life at Mixel At Mixel, a Silvaco company, we believe in empowering our people and meeting them where they are in their careers. Our Total Rewards package is designed to reflect the local culture and community where our employees live and work — because we know success starts with feeling valued and supported. Our people are our greatest strength. We also believe in a pay-for-performance philosophy — rewarding impact, recognizing achievements, and providing security for the future. Here are some of the key highlights: · Competitive pay · Annual and spot bonuses · Long-term incentive plan awards (RSUs) · Health benefits · Paid holidays and time off · Various learning and leadership opportunities

Responsibilities

Develop test plans and architect system-level verification environments using UVM-based testbenches. Drive functional and code coverage closure while supporting FPGA-based prototyping and pre-silicon bring-up.