WHAT MAKES YOU A GREAT FIT:

• 5+ years of experience in Digital Verification at a major semiconductor or EDA tool company
• Experience working on DRAM, Memory Controllers, ASICS, or MCUs
• Proven expertise in all areas of the end-to-end design verification workflow for function coverage, including design document review, feature extraction, test plan creation, stimulus generation, testbench creation, and test suite creation
• Advanced proficiency in SystemVerilog and UVM Methodology
• Proficiency with EDA verification tools like vManager, Xcelium, Jasper, etc.
• Experience in creating and testing with Verification IPs
• Excellent written and spoken communication skills

As a Digital Verification Engineer at Normal Computing, you will bring your expertise in the end-to-end design verification flow for functional coverage by supporting our Verification AI team and building testbench environments from design documents to support product development.

Overview & Responsibilities

• Reviewing chip documentation to develop test plans, test suites, coverage code, and testbenches.
• Setting up EDA tools and vendor-specific chip design tools on shared computing resources.
• Speaking with customers to conduct user research and participate in Normal’s technical sales effort.
• Partnering with our internal hardware, product, and machine learning teams to provide expertise on a variety of design verification projects.
• Working with contractors to acquire and produce high-quality design verification collateral.