Digital Verification Engineer (Specman) – Semiconductor (all gender) at Alten

Munich, Bavaria, Germany -

Full Time

Start Date

Immediate

Expiry Date

06 Jan, 26

Salary

0.0

Posted On

08 Oct, 25

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Digital Functional Verification, System Verilog, System Verilog Assertions, UVM Methodology, Specman, Python, Perl, RTL, Gatelevel Code, Communication Skills, Mixed-Signal Designs, Formal Verification, Functional Verification, Testbenches, Assertions, Collaboration

Industry

Engineering Services

Description

Company Description We are the designers of today for the world of tomorrow. As one of the world's leading engineering service providers, we at ALTEN are committed to positively shaping the future of our partners, the careers of our employees and the challenges facing our society and environment. More than 50,000 employees in 30 countries are already working on innovative solutions in various engineering and IT sectors such as automotive, aerospace, renewable energy, medical technology and railway technology. Job Description YOU… verify mixed-signal designs on block and system level resting upon formal and functional verification interpret product requirements to create the verification concept and the product verification specification perform random-constraint testbenches according to the state of the art create assertions to prove the design using formal methods work in collaboration with lab and test engineers, designers, system architects, and verification engineers across multiple sites Qualifications YOU… have completed engineering degree in electrical engineering, computer science or similar studies already have practical experience in the field of digital functional verification and common safety standards have extensive programming skills in coding in System Verilog and System Verilog assertions have good knowledge of UVM methodology and Specman - e language, scripting languages like Python or Perl and ability to interpret RTL and Gatelevel code have good communication skills in English We value diversity and therefore welcome all applications - regardless of gender, nationality, ethnic and social origin, religion/belief, disability, age and sexual orientation and identity. Severely disabled persons will be given preferential consideration if they are equally qualified. Do you have any questions? Then contact me: Özlem Mumin (Tel.: +49 89 255552-331) Or apply now using our online application form. Additional Information Talent Management - we develop your career Work life balance - flexible working hours and mobile working possible Fit and relaxed – with EGYM Wellpass Enjoy biking – always on tour with bike leasing Green Mobility - with us you can travel at a reduced rate ...in addition we offer a permanent employment contract, corporate benefits and team events.

Responsibilities

The Digital Verification Engineer will verify mixed-signal designs on block and system levels, focusing on formal and functional verification. They will collaborate with various engineering teams to interpret product requirements and create verification concepts.