Digital Verification Manager / Sr Manager at Silvaco

Cairo, Cairo, Egypt -

Full Time

Start Date

Immediate

Expiry Date

23 Aug, 26

Salary

0.0

Posted On

25 May, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

UVM, System Verilog, Digital Verification, Mixed Signal Verification, AMS Co-simulation, Formal Verification, Assertion-Based Verification, Python, Perl, TCL, Shell Scripting, VLSI Design, RTL Synthesis, People Management, Technical Leadership, Gate-level Simulation

Industry

Software Development

Description

Company Description Mixel, a Silvaco Company, is an innovator of high-performance analog mixed signal semiconductor IPs whose solutions are powering Mobile, Display, Camera, Automotive, VR, AR and AI applications. Our mission is to provide our customers and partners with outstanding mixed-signal, silicon-proven IPs, creating in the process a differentiating technology that sets your products apart. At Mixel, you will find an inspiring environment with a strong focus on technical innovation, people well-being, no layers of management, and the freedom to make meaningful contributions in a setting that encourages creative thinking. We value open communication, empathy, mutual trust, and respect. Job Description Technical Leadership Role: Define and own the end-to-end verification strategy, including planning, coverage closure, and sign-off criteria. Architect and own the development of reusable UVM-based environments for different digital and mixed signal IPs verification Drive adoption and continuous improvement of verification methodologies (UVM, formal verification, etc.) Oversee AMS co-simulation strategies using real-number modeling and behavioral analog models Ensure comprehensive verification of different modes of operation including protocol corner cases, training sequences, error injection and recovery, loopback and test modes Implement assertion-based verification for calibration and training correctness Stay current with industry trends and emerging verification tools and technologies, driving their adoption where applicable Program Execution: Collaborate closely with RTL design, architecture, and mixed signal design teams to ensure seamless integration and verification of IP blocks Own verification schedules, resource planning, and risk mitigation across concurrent projects Engage with customers and partners on IP deliverables, verification collateral, and integration support Represent the verification team in program reviews, milestone sign-offs, and customer-facing discussions Establish and track KPIs and quality metrics for verification completeness and team productivity People and Team Management: Lead, mentor and grow the verification team Drive hiring, onboarding, performance reviews, and career development plans Foster a culture of technical excellence, peer review, knowledge sharing, and continuous improvement Drive team motivation through clear vision-setting, timely recognition of achievements, and visible support during critical project phases Allocate resources across multiple concurrent IP projects, balancing schedules, skill sets, and priorities Qualifications Essential Qualifications and Experience: Bachelor's or Master's degree in Electrical Engineering or Computer Engineering 12+ Years of experience in VLSI Digital Design/Verification, with 3-5+ years in a people management or technical lead role Proven track record of taking IPs from spec to silicon-proven delivery Strong command of UVM and System Verilog; constrained-random verification, coverage-driven verification, and assertion-based verification Experience with gate-level simulation, X-propagation, and SDF back-annotation flows Solid understanding of mixed signal verification including real number modeling, behavioral modeling and AMS co-sim Experience verifying analog-digital interface boundaries, and calibration logic Strong understanding of Verilog RTL design techniques and tradeoffs Solid understanding of ASIC/FPGA design flows including RTL Synthesis, place and route, and timing sign-off Strong knowledge of Python/Perl/TCL/Shell scripting languages Experience working with global teams Desirable Qualifications and Experience: Knowledge of clock and reset domain crossing techniques Familiarity with ISO 26262 or other functional safety standards Experience using version control tools, and bug tracking software Familiarity with SERDES PHYs and Protocols Additional Information Life at Mixel At Mixel, a Silvaco company, we believe in empowering our people and meeting them where they are in their careers. Our Total Rewards package is designed to reflect the local culture and community where our employees live and work — because we know success starts with feeling valued and supported. Our people are our greatest strength. We also believe in a pay-for-performance philosophy — rewarding impact, recognizing achievements, and providing security for the future. Here are some of the key highlights: · Competitive pay · Annual and spot bonuses · Long-term incentive plan awards · Health benefits · Paid holidays and time off · Various learning and leadership opportunities

Responsibilities

Define and own the end-to-end digital and mixed-signal verification strategy, including the development of reusable UVM-based environments. Lead and mentor the verification team while collaborating with RTL and architecture teams to ensure silicon-proven IP delivery.