Director, ASIC Physical Design at Ayar Labs

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

25 Aug, 26

Salary

0.0

Posted On

27 May, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC Physical Design, RTL2GDS, Static Timing Analysis, 3DIC Integration, SoC Integration, Synthesis, Place and Route, EMIR, DFT, LVS, DRC, Team Leadership, Vendor Evaluation, Analog and Digital Integration, Silicon Photonics, SerDes IP

Industry

Computer Hardware Manufacturing

Description

Director, ASIC Physical Design Location: Bengaluru (on-site, flexible hours) Ayar Labs is seeking a Director of ASIC Physical Design to develop and tape out the next generation of electronic-photonic integrated chips. The candidate will be responsible for leading the ASIC integration team, performing design integration, physical design, and tapeouts of ICs containing custom analog, photonic, and digital subsystems implemented in both 3DIC and specialty platforms. The ideal candidate will be a mission-driven team leader with management and leadership experience in product-focused organizations, with a comprehensive silicon development background, a track record of first-silicon successes, and eagerness to apply specialized ASIC skillsets to a wide range of problems. Essential Functions: * Manage and grow the skillsets of an experienced ASIC integration team which has successfully taped out multiple generations of Ayar Labs SoCs * Drive timely execution of both test chip and product tapeouts * Develop and improve upon complex SoC integration flows integrating photonics, circuits, advanced nodes, and 3DIC integration in leading edge nodes * Oversee digital-top physical design and RTL2GDS flows: synthesis, place and route, and static timing analysis * Drive clear and effective decision-making across multiple functions and teams within the organization * Implement SoC signoff and cross-check methodologies to deliver high-quality tapeouts incorporating a wide range of disciplines * Maintain EDA infrastructure for the broader design organization Basic Qualifications: * BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related fields * 12+ years of experience in ASIC development and tapeouts * 5+ years of Experience leading teams of both local and remote engineers through successful tapeouts in multiple leading edge technologies * Experience driving tool and IP vendor evaluation and selection * Strong problem solving skills and demonstrated ability to apply known methodologies towards new problems * Expert in a broad set of ASIC flows and methodologies: RTL2GDS, EMIR, DFT, STA, LVS, DRC, LIB/LEF * Experience working with integration of analog and digital components into SoC's * Passionate about developing and enhancing build flows, methodologies, and automation * Strong communicator and team-builder who can drive cross-functional alignment Preferred Qualifications: * Experience with design or implementation of SerDes IP block interfaces in a complex SoC fabric environment * Core knowledge of semiconductor physics * Working knowledge of optics and silicon photonics NOTE TO RECRUITERS: Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.

Responsibilities

Lead the ASIC integration team to develop and tape out next-generation electronic-photonic integrated chips. Oversee digital-top physical design, RTL2GDS flows, and SoC signoff methodologies across multiple functions.