DIRECTOR OF SOC / ASIC INTEGRATION

Ayar Labs is seeking a Director of SoC / ASIC integration to develop and tape out the next generation of electronic-photonic integrated chips. The candidate will be responsible for leading the ASIC integration team, performing design integration, physical design, and tapeouts of ICs containing custom analog, photonic, and digital subsystems implemented in both 3DIC and specialty platforms. The ideal candidate will be a mission-driven team leader with management and leadership experience in product-focused organizations, with a comprehensive silicon development background, a track record of first-silicon successes, and eagerness to apply specialized ASIC skillsets to a wide range of problems.

BASIC QUALIFICATIONS:

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related fields
• 10+ years of experience in ASIC development and tapeouts
• 5+ years of Experience leading teams of both local and remote engineers through successful tapeouts
• Experience driving tool and IP vendor evaluation and selection
• Strong problem solving skills and demonstrated ability to apply known methodologies towards new problems
• Expert in a broad set of ASIC flows and methodologies: RTL2GDS, EMIR, DFT, STA, LVS, DRC, LIB/LEF
• Experience working with integration of analog and digital components into SoC’s
• Passionate about developing and enhancing build flows, methodologies, and automation
• Strong communicator and team-builder who can drive cross-functional alignment

PREFERRED QUALIFICATIONS:

• Experience with design or implementation of SerDes IP block interfaces in a complex SoC fabric environment
• Experience working through issues in speciality or immature process technologies
• Core knowledge of semiconductor physics
• Working knowledge of optics and silicon photonics
  Salary range: $220,000 - $275,000

• Manage and grow the skillsets of an experienced ASIC integration team which has successfully taped out multiple generations of Ayar Labs SoCs
• Drive timely execution of both test chip and product tapeouts
• Develop and improve upon complex SoC integration flows integrating photonics, circuits, advanced nodes, and 3DIC integration
• Oversee digital-top physical design and RTL2GDS flows: synthesis, place and route, and static timing analysis
• Drive clear and effective decision-making across multiple functions and teams within the organization
• Implement SoC signoff and cross-check methodologies to deliver high-quality tapeouts incorporating a wide range of disciplines
• Maintain EDA infrastructure for the broader design organization