Distributed Training & Performance Engineer - Executive Director at JPMC Candidate Experience page

New York, New York, United States -

Full Time

Start Date

Immediate

Expiry Date

07 May, 26

Salary

0.0

Posted On

06 Feb, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Distributed Systems, Performance Engineering, CUDA, Triton, Python, C++, GPU Programming, Kernel Optimization, Data Parallelism, Tensor Parallelism, Pipeline Parallelism, Memory Sharding, Profiling, Optimization, Machine Learning, Large-Scale Training

Industry

Financial Services

Description

Are you looking for an exciting opportunity to join a dynamic and growing team in a fast paced and challenging area? This is a unique opportunity for you to work with Global Technology Applied Research (GTAR) center at JPMorganChase. The goal of GTAR is to design and conduct research across multiple frontier technologies, in order to enable novel discoveries and inventions, and to inform and develop next-generation solutions for the firm’s clients and businesses. As a senior-level engineer in the Global Technology Applied Research (GTAR) center you will design, optimize, and scale large-model pretraining workloads across hyperscale accelerator clusters. This role sits at the intersection of distributed systems, kernel-level performance engineering, and large-scale model training. The ideal candidate can take a fixed hardware budget (accelerator type, node topology, interconnect, and cluster size) and design efficient, stable, and scalable training strategy, spanning parallelism layout, memory strategy, kernel optimization, and end-to-end system performance. This is a hands-on role with direct impact on training throughput, efficiency, and cost at scale. Job responsibilities Design and optimize distributed training strategies for large-scale models, including data, tensor, pipeline, context parallelism. Manage end-to-end training performance: from data input pipelines through model execution, communication, and checkpointing. Identify and eliminate performance bottlenecks using systematic profiling and performance modeling. Develop or optimize high-performance kernels using CUDA, Triton, or equivalent frameworks. Design and optimize distributed communication strategies to maximize overlap between computation and inter-node data movement. Design memory-efficient training configurations (caching, optimizer sharding, checkpoint strategies). Evaluate and optimize training on multiple accelerator platforms, including GPUs and non-GPU accelerators. Contribute towards incorporating performance improvements back to internal pipelines. Required qualifications, capabilities, and skills Master’s degree with 5+ years of industry experiences, or Ph.D. degree with 3+ years of industry experience in computer science, physics, math, engineering or related fields. Engineering experience at top AI labs, HPC centers, chip vendors, or hyperscale ML infra teams. Strong experience designing and operating large-scale distributed training jobs across multinode accelerator clusters. Deep understanding of distributed parallelism strategies: data parallelism, tensor/model parallelism, pipeline parallelism, and memory/optimizer sharding. Proven ability to profile and optimize training performance using industry standard tools such as Nsight, PyTorch profiler, or equivalent. Hands-on experience with GPU programming and kernel optimization. Strong understanding of accelerator memory hierarchies, bandwidth limitations, and compute-communication tradeoffs. Experience with collective communication libraries and patterns (e.g., NCCL-style collectives). Proficiency in Python for ML systems development and C++ for performance-critical components. Experience with modern ML frameworks such as PyTorch or JAX in large-scale training settings. Preferred qualifications, capabilities, and skills Experience optimizing training workloads on non-GPU accelerators (e.g., TPU, or wafer-scale architectures). Familiarity with compiler-driven ML systems (e.g., XLA, MLIR, Inductor) and graph-level optimizations. Experience designing custom fused kernels or novel execution strategies for attention or large matrix operations. Strong understanding of scaling laws governing large-model pretraining dynamics and stability considerations. Contributions to open-source ML systems, distributed training frameworks, or performance-critical kernels. Prior experience collaborating directly with hardware vendors or accelerator teams. JPMorganChase, one of the oldest financial institutions, offers innovative financial solutions to millions of consumers, small businesses and many of the world’s most prominent corporate, institutional and government clients under the J.P. Morgan and Chase brands. Our history spans over 200 years and today we are a leader in investment banking, consumer and small business banking, commercial banking, financial transaction processing and asset management. We offer a competitive total rewards package including base salary determined based on the role, experience, skill set and location. Those in eligible roles may receive commission-based pay and/or discretionary incentive compensation, paid in the form of cash and/or forfeitable equity, awarded in recognition of individual achievements and contributions. We also offer a range of benefits and programs to meet employee needs, based on eligibility. These benefits include comprehensive health care coverage, on-site health and wellness centers, a retirement savings plan, backup childcare, tuition reimbursement, mental health support, financial coaching and more. Additional details about total compensation and benefits will be provided during the hiring process. We recognize that our people are our strength and the diverse talents they bring to our global workforce are directly linked to our success. We are an equal opportunity employer and place a high value on diversity and inclusion at our company. We do not discriminate on the basis of any protected attribute, including race, religion, color, national origin, gender, sexual orientation, gender identity, gender expression, age, marital or veteran status, pregnancy or disability, or any other basis protected under applicable law. We also make reasonable accommodations for applicants’ and employees’ religious practices and beliefs, as well as mental health or physical disability needs. Visit our FAQs for more information about requesting an accommodation. JPMorgan Chase & Co. is an Equal Opportunity Employer, including Disability/Veterans The Chief Technology Office oversees enabling components inclusive of the top quality engineering and architecture tools and practices, key program management and processes as well as the technology workforce strategy required to make us a leading technology company for our customers, clients and colleagues around the world. High Risk Roles (HRR) are sensitive roles within the technology organization that require high assurance of the integrity of staff by virtue of 1) sensitive cybersecurity and technology functions they perform within systems or 2) information they receive regarding sensitive cybersecurity or technology matters. Users in these roles are subject to enhanced pre-hire screening which includes both criminal and credit background checks (as allowed by law). The enhanced screening will need to be successfully completed prior to commencing employment or assignment.

Responsibilities

Design and optimize distributed training strategies for large-scale models, managing end-to-end training performance. Identify and eliminate performance bottlenecks while developing high-performance kernels and optimizing distributed communication strategies.