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DMTS Product Architect at Micron Technology

San Jose, California, United States -

Full Time

Start Date

Immediate

Expiry Date

19 Feb, 26

Salary

0.0

Posted On

21 Nov, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

System Architecture, Memory Technologies, DRAM, AI Applications, High-Performance Computing, Mentoring, LPDDR, DDR, HBM, Memory Hierarchy, Memory Controllers, PHY Design, SoC Design, HW/SW Co-Optimization, JEDEC Standards, Packaging Technologies

Industry

Semiconductor Manufacturing

Description

Working closely with Product and Business Development Managers you will ensure that each technical decision is aligned with our business strategy and ultimately help bring these outstanding new products to our customers! Conduct system architecture exploration, analysis, and evaluation using modeling, simulation, and prototyping tools. Collaborate with customers and external partners to identify architecture bottlenecks and propose innovative solutions. Drive pathfinding initiatives for system architectures incorporating LPDDR, DDR, and HBM memory technologies. Explore memory features that enhance DRAM's value proposition in AI and high-performance computing applications. Mentor and coach junior system architects and engineers to build technical expertise within the team. Bachelor's degree in Electrical Engineering or related field (BSEE or higher). 12+ years of experience in system design and architecture. Strong understanding of memory hierarchy, memory controllers, and PHY design. Familiarity with LPDDR, DDR, and HBM memory technologies and their integration in compute systems. Ability to work independently and collaboratively in a fast-paced, dynamic environment. Master's or Ph.D. in Electrical Engineering, Computer Engineering, or related discipline. Deep knowledge of memory architectures, system memory hierarchy, and compute system architectures. Exposure to packaging technologies such as TSV, stacked packaging, and 3D packaging. Experience with custom SoC/ASIC design and HW/SW co-optimization. Understanding of JEDEC standards and participation in specification-setting processes; familiarity with AI frameworks and high-performance computing applications.

Responsibilities

The role involves ensuring technical decisions align with business strategy and conducting system architecture exploration and evaluation. You will collaborate with customers and partners to identify bottlenecks and propose innovative solutions.