DRAM Circuit Designer, up to Staff at Qualcomm Technologies International Ltd

Hsinchu, , Taiwan -

Full Time

Start Date

Immediate

Expiry Date

12 Jul, 26

Salary

0.0

Posted On

13 Apr, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

DRAM circuit design, Mixed-signal design, Memory architecture, Layout design, Circuit simulation, Verilog, Verilog-A, Verilog-AMS, Matlab, Python, High-speed design, Dataflow modeling, 2.5D/3D integration, ASIC design, Power delivery design, Timing control

Industry

Semiconductor Manufacturing

Description

Company: Qualcomm Semiconductor Limited Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm Overview: Qualcomm is a company of inventors that unlocked edge AI and connected computing ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform high performance AI and connected computing potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. General Summary: Job Overview: The Qualcomm Memory System/Technology Team in Process & Package Solutions Group has an opening in the areas of custom DRAM design and architecture for memory-centric compute systems for data center, mobile, compute, and XR. The candidate will design circuits for the custom DRAM to improve system KPIs such as bandwidth, latency, power, thermal, and area efficiency. The candidate will work on solutions addressing manufacturability and repairability of the circuits. The candidate is expected to know the DRAM circuit design in the domains of DRAM bank circuits such as decoder, sense amplifier, datapath, and voltage generation circuits. The candidate should have familiarity with the bus and compute fabrics as well as advanced packaging and 3D integration. This position offers the opportunity to work across multiple organizations such as process and packaging team, AI and compute architects, memory controller team, global SoC team, and emulation team. Providing timely feedback and updating architecture and design trade-offs to the team is essential. Responsibilities: Design and optimize memory core circuits for higher sense margin, improved array timing, area Develop and optimize DRAM circuits and timing control for performant, area, and energy efficient cell array Develop bank array placement strategies across various bank array, TSV, and power distribution choices Develop novel fabrics for best/robust distribution of high-bandwidth busses across the DRAM array, compute, and IO Create layouts that optimize circuit placement, signal routing, and power delivery Develop robust power delivery to the array design Use state-of-the-art design and simulation tools to simulate the circuit behavior and manufacturability readiness Develop behavioral, timing, and power models of the circuits to guide the architecture choices across AI, compute, and mobile workloads Floorplan DRAM circuits under manufacturing constraints, testability, repairability, and high performance Minimum Qualifications: Experience in mixed-signal design, layout, and simulation Knowledge of high-speed design principles and reliability Experience in memory array and datapath design (SRAM/DRAM/Flash/ROM/OPT, etc) Ability to develop Verilog/Verilog-A/Verilog-AMS models of critical dataflow is strong plus Proficiency in use of EDA tools, Matlab, and Phyton Good knowledge of memory architecture, buses, and 2.5D/3D integration Master's or Ph.D. in Electrical Engineering and a related field Preferred Qualifications: Experience in DRAM architecture performance assessment Experience in programming language (C/C++/Phyton) or scripting language (Perl/Python) Familiar with the DRAM datasheets and IO interfaces Soft Skills: Self-Starter with good communication skills and team-working spirit Strong problem-solving and analytical skills Ability to work independently and as part of a team Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

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Responsibilities

Design and optimize memory core circuits, including bank array placement and high-bandwidth bus fabrics, to improve system performance, power, and area efficiency. Develop behavioral and power models to guide architecture choices and ensure manufacturability, testability, and repairability of the designs.