Y-Axis Jobs Logo
Send us feedback
telephone  +91 7670 800 001
Log in Sign up Try Premium
DRAM Design Senior Layout Engineer at Micron Technology
Tlaquepaque, jalisco, Mexico -
Full Time

Start Date

Immediate

Expiry Date

07 Mar, 26

Salary

0.0

Posted On

07 Dec, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

DRAM Design, Layout Verification, LVS, DRC, EM, Analog Layout Designs, CMOS Process, IP Layout Development, Physical Verification, Cadence Tools, Virtuoso, Device Matching, Parasitic Analysis, Electron Migration, Isolation Techniques, Layout Fundamentals

Industry

Semiconductor Manufacturing

Description
Responsible for Design and development of IP layouts used in DRAM chips. Perform layout verification like LVS/DRC/EM, quality check and documentation. Responsible for timely delivery of block-level layouts with acceptable quality. Guide and lead unexperienced team-members in their execution of Sub block-level layouts & review their work. Must have at least 5 years of validated experience in analog layout designs in CMOS process. Experience performing IP layout development and physical verification activities for complex designs as per provided specs. Should have solid knowledge of the layout area and routing optimization, design rules, yield and reliability issues. Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques. Should have adequate knowledge of schematics, collaborating with circuit design and CAD team Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc. Understanding layout effects on the circuit such as speed, capacitance, power and area. Bachelor's, Master's, PhD or equivalent in Electronics, Physics, Electricity or related.
Responsibilities
Responsible for the design and development of IP layouts used in DRAM chips, including layout verification and quality checks. Guide and lead inexperienced team members in executing sub block-level layouts and reviewing their work.