DRAM Memory Design Engineer, Principal | MST | SMTS at Micron Technology

Boise, Idaho, United States -

Full Time

Start Date

Immediate

Expiry Date

05 Jan, 26

Salary

0.0

Posted On

07 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Dram Sub-System Architecture, CMOS Circuit Design, VLSI, Analog Circuit Design, Cadence Virtuoso, Physical Layout, Circuit Floor Planning, FINESIM, HSPICE, VERILOG, Device Reliability, Problem-Solving, Analytical Skills, Design Validation, Innovation, Cross-Group Communication

Industry

Semiconductor Manufacturing

Description

Responsibilities include managing project activities, maintaining technical expertise through cross-group communication and training, and driving innovation in future memory generations. Contribute to the Design and Layout of New Memory Products Implement device specifications and develop circuit solutions. Design digital and analog circuits using CMOS logic gates and transistors. Design memory core circuits and optimize for sense margins, array timings, and die size. Prepare design documentation for other engineers. Analyze circuits for power consumption, speed performance, and reliability. Assist with design validation, reticle experiments, and necessary tape-out revisions. Manage design and layout resource allocations. Serve as the point of contact for design, layout, verification, and testing issues. Monitor progress and track tasks. Prepare project status reports for upper management. Plan and hold design reviews to discuss project progress and decisions. Contribute to cross group communication to work towards standardization and group success Aid in design documentation and communicating best known practices to entire department Participate in continuing education and competitor analysis Proactively solicit feedback from Standards, CAD, modeling, and verification groups to ensure the design quality Drive innovation into the future Memory generations within a dynamic work environment Course work in CMOS Circuit Design, VLSI, and Analog Circuit Design Knowledge and experience using Cadence Virtuoso Understanding Physical Layout & Circuit Floor Planning Experience simulating with FINESIM, HSPICE and VERILOG Understanding of Device Reliability Excellent problem-solving and analytical skills Expertise in DRAM sub-system architecture, specification, operation, or design Experience leading technical projects across departments Proven significant technical contributions and a consistent record of innovation BS or MS in Electrical Engineering or related field plus 10 years of experience in DRAM design, product, or system.

Responsibilities

The role involves managing project activities and driving innovation in future memory generations. Responsibilities also include contributing to the design and layout of new memory products and preparing design documentation for other engineers.