DSP - FEC Design Engineer at Celero Communications, Inc.

Vancouver, British Columbia, Canada -

Full Time

Start Date

Immediate

Expiry Date

15 Jun, 26

Salary

250000.0

Posted On

17 Mar, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Coding Theory, Digital Communications, Error Correction Techniques, FEC Algorithms, LDPC, Staircase Codes, Simulation, C/C++, Python, MATLAB, ASIC Implementation, Verilog, VHDL, DSP, Optical Transceivers, Algorithm Design

Industry

Telecommunications

Description

About the Role: Celero Communications Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. We are looking for skilled and motivated engineers to join our team and help us build optical transceivers for next-generation optical modems. The ideal candidate must have a strong theoretical background in coding theory, digital communications, and error correction techniques, with experience developing high-performance forward error correction (FEC) algorithms for high-speed communication systems. Candidates with industry experience are preferred. Key Responsibilities Research, develop, and evaluate forward error correction (FEC) schemes for high-speed optical communication systems. Design and optimize soft-decision FEC algorithms suitable for high-throughput optical modem implementations. Develop and evaluate coding schemes such as LDPC, staircase codes, or related high-performance FEC architectures. Model and simulate FEC performance in optical communication systems, including interaction with DSP blocks and channel impairments. Analyze performance trade-offs including coding gain, latency, throughput, and implementation complexity. Develop floating-point and fixed-point simulation models for algorithm verification. Implement bit-accurate and cycle-accurate models supporting ASIC implementation. Collaborate closely with DSP, ASIC, firmware, and verification teams to ensure efficient hardware implementation. Document algorithm design and simulation results. Preferred Qualifications Master’s or Ph.D. degree in Electrical Engineering, Mathematics, Computer Engineering, or related field. Strong background in coding theory and error correction algorithms. Experience with FEC schemes for communication systems, particularly soft-decision FEC. Familiarity with LDPC, staircase codes, product codes, or related modern FEC techniques. Experience evaluating coding gain, BER performance, and decoder complexity. Programming experience in C/C++, Python, MATLAB, or similar languages. Experience in modeling communication systems. Familiarity with DSP algorithms for communication systems. Experience with version control systems, specifically GitHub. Familiarity with hardware implementation considerations and languages such as Verilog or VHDL is a plus. Team player with a mindset focused on the successful delivery of the first product. Why Join Us The chance to play a foundational role at a high-growth semiconductor start-up. Work on cutting-edge optical communication technologies powering AI and hyperscale data centers. A collaborative, international team culture where ideas and initiative are valued. The opportunity to grow alongside Celero as we scale and shape the future of our industry. Salary Range $150,000 - $250,000 Base Annually The final offer will be determined based on job-related skills, experience, qualifications, and location.

Responsibilities

The role involves researching, developing, and optimizing forward error correction (FEC) schemes, such as LDPC and staircase codes, for high-speed optical communication systems. Key tasks include modeling and simulating FEC performance, developing bit-accurate models, and collaborating with cross-functional teams for efficient hardware implementation.