DV SV UVM_DRAM at Quest Global

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

16 Mar, 26

Salary

0.0

Posted On

16 Dec, 25

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Design Verification, SystemVerilog, UVM, Testbench Development, Debugging, Functional Coverage, Scripting, Protocol Verification, EDA Tools, Object-Oriented Programming, Constrained-Random Testing, Assertion-Based Verification, Root Cause Analysis, Regression Suites, Automation, Low-Power Verification

Industry

Engineering Services

Description

Job Requirements ob Title Design Verification Engineer Job Description Job Summary We are seeking a talented and detail-oriented Design Verification Engineer to join our core team. As a DV Engineer, you will play a crucial role in ensuring the functional correctness and quality of complex IP blocks and subsystems. This role requires a deep understanding of modern verification methodologies. You will be responsible for developing sophisticated, reusable verification environments from scratch using SystemVerilog and the Universal Verification Methodology (UVM). Key Responsibilities Analyze design specifications and collaborate with architects and RTL designers to develop comprehensive, coverage-driven verification plans. Architect, develop, and maintain robust, scalable, and reusable UVM-based testbench environments. Implement key testbench components, including UVM agents (drivers, monitors), scoreboards, and sequences. Develop and execute a mix of constrained-random and directed test cases to thoroughly validate design functionality and hit complex corner cases. Debug RTL and testbench failures, performing deep root cause analysis using waveforms and logs, and work with designers to resolve issues. Define and implement functional coverage models (covergroups) and assertion-based checks (SVA) to measure the effectiveness of the verification effort. Analyze coverage reports, identify verification gaps, and develop strategies to achieve 100% coverage closure. Enhance and maintain regression suites and automate verification flows using scripting languages to improve efficiency. Required Qualifications & Skills Education: Bachelor’s or Master’s degree in Electrical Engineering (EE), Computer Engineering (CE), or a related discipline. Experience: 3+ years of direct, hands-on experience in ASIC/SoC design verification. SystemVerilog Expertise: Expert-level proficiency in SystemVerilog, including a strong grasp of Object-Oriented Programming (OOP) concepts, constrained-random stimulus generation, and assertion-based verification (SVA). UVM Mastery: Deep, practical experience with the Universal Verification Methodology (UVM). This includes building complete testbenches with agents, sequencers, scoreboards, and leveraging the UVM factory and configuration database. Verification Fundamentals: Solid understanding of modern verification principles, including coverage-driven methodologies, test planning, and advanced debug techniques. Protocol Knowledge: Hands-on experience verifying at least one standard industry protocol such as AXI, AHB, PCIe, DDR, Ethernet, or similar. Tools: Proficiency with industry-standard EDA simulation tools like Synopsys VCS, Cadence Xcelium, or Siemens Questa. Scripting: Strong scripting skills in a language like Python, Perl, or Tcl for automation. Preferred/Desired Qualifications Experience with C/C++ for creating reference models or for co-simulation environments. Familiarity with formal verification techniques and tools. Experience with Gate-Level Simulations (GLS) and debugging timing-related issues. Knowledge of low-power verification techniques (UPF). Prior experience contributing to post-silicon validation and debug. Required Skills and Experience Job Summary We are seeking a talented and detail-oriented Design Verification Engineer to join our core team. As a DV Engineer, you will play a crucial role in ensuring the functional correctness and quality of complex IP blocks and subsystems. This role requires a deep understanding of modern verification methodologies. You will be responsible for developing sophisticated, reusable verification environments from scratch using SystemVerilog and the Universal Verification Methodology (UVM). Key Responsibilities Analyze design specifications and collaborate with architects and RTL designers to develop comprehensive, coverage-driven verification plans. Architect, develop, and maintain robust, scalable, and reusable UVM-based testbench environments. Implement key testbench components, including UVM agents (drivers, monitors), scoreboards, and sequences. Develop and execute a mix of constrained-random and directed test cases to thoroughly validate design functionality and hit complex corner cases. Debug RTL and testbench failures, performing deep root cause analysis using waveforms and logs, and work with designers to resolve issues. Define and implement functional coverage models (covergroups) and assertion-based checks (SVA) to measure the effectiveness of the verification effort. Analyze coverage reports, identify verification gaps, and develop strategies to achieve 100% coverage closure. Enhance and maintain regression suites and automate verification flows using scripting languages to improve efficiency. Required Qualifications & Skills Education: Bachelor’s or Master’s degree in Electrical Engineering (EE), Computer Engineering (CE), or a related discipline. Experience: 3+ years of direct, hands-on experience in ASIC/SoC design verification. SystemVerilog Expertise: Expert-level proficiency in SystemVerilog, including a strong grasp of Object-Oriented Programming (OOP) concepts, constrained-random stimulus generation, and assertion-based verification (SVA). UVM Mastery: Deep, practical experience with the Universal Verification Methodology (UVM). This includes building complete testbenches with agents, sequencers, scoreboards, and leveraging the UVM factory and configuration database. Verification Fundamentals: Solid understanding of modern verification principles, including coverage-driven methodologies, test planning, and advanced debug techniques. Protocol Knowledge: Hands-on experience verifying at least one standard industry protocol such as AXI, AHB, PCIe, DDR, Ethernet, or similar. Tools: Proficiency with industry-standard EDA simulation tools like Synopsys VCS, Cadence Xcelium, or Siemens Questa. Scripting: Strong scripting skills in a language like Python, Perl, or Tcl for automation. Work Experience Preferred/Desired Qualifications Experience with C/C++ for creating reference models or for co-simulation environments. Familiarity with formal verification techniques and tools. Experience with Gate-Level Simulations (GLS) and debugging timing-related issues. Knowledge of low-power verification techniques (UPF). Prior experience contributing to post-silicon validation and debug.

Responsibilities

The Design Verification Engineer will analyze design specifications and collaborate with architects and RTL designers to develop comprehensive verification plans. They will also architect, develop, and maintain UVM-based testbench environments and debug RTL and testbench failures.