MINIMUM QUALIFICATIONS:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of technical experience in physical design disciplines involving power delivery and advanced process technology nodes.
• Experience with power grid integrity (EMIR) from budgeting to analysis to verification and signoff.
• Experience using EMIR tools (e.g., RedHawk-SC, Totem, Voltus).

PREFERRED QUALIFICATIONS:

• Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience owning EMIR at the block or full-chip level, including proactive floorplanning and defining standard cell usage with physical design owners.
• Experience establishing EMIR budgets, defining signoff methodologies, and bringing up EMIR flows for new projects.
• Experience with power delivery voltage droop mitigation
• Knowledge of low power design techniques (e.g., multiple threshold voltage/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling).

• Drive Electromigration and IR Drop (EMIR) analysis at the block, sub-chip and full-chip levels, including running signoff checks.
• Collaborate with physical design tool/flow owners on EMIR mitigation strategies such proactive floor planning and optimal selection of standard cells.
• Collaborate with the physical design, strategy and technology acceleration (STA), package, and circuit/technology teams to define project EMIR budgets, margins and signoff methodologies.
• Work with internal teams and external vendors to bring up EMIR tools (e.g., RedHawk-SC, Totem, Voltus) for new projects.
• Contribute to flows, checkers, reporting and any tooling around signoff.
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