Emulation Verification Engineer at Apple

San Diego, California, United States -

Full Time

Start Date

Immediate

Expiry Date

20 Jan, 26

Salary

0.0

Posted On

22 Oct, 25

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Emulation, Verification, Wireless SoCs, Mixed Signal Models, Palladium, System Verilog, Verilog, UVM, Debugging, Design Verification, Silicon Validation, SystemVerilog Assertions, Scripting, Low Power Methodologies, UVM Acceleration

Industry

Computers and Electronics Manufacturing

Description

Imagine what you could at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Are you passionate about changing the world? We have a critical impact on getting high quality functional products to millions of customers quickly. We are looking for you to join our Emulation team focusing on the creation, deployment, and support of advanced emulation environments. In this highly visible role, you will be at the center of a chip design effort collaborating with all disciplines. Are you ready to help us deliver the next groundbreaking Apple products? DESCRIPTION As a member of Emulation Verification team, you will play a key role in utilizing Emulation for verification of large Wireless SoCs. You will also be involved in the most cutting-edge technology of bringing in mixed signal models onto the Palladium platform. The overall work will involve porting the design onto the Palladium platform, followed by executing the detailed Emulation testplan. MINIMUM QUALIFICATIONS BS and a minimum of 3 years of relevant industry experience. Experience with System Verilog, Verilog or UVM. PREFERRED QUALIFICATIONS Experience with bring up, debugging and verification in Emulation. Understanding of the tool flow from RTL to Emulation. Good understanding of any Standard Emulator (Palladium, Veloce, Zebu) OR FPGA (Xilinx, Altera) flow. Proven Design Verification or Silicon Validation skills. Experience in writing Synthesize-able SystemVerilog/Verilog code and SystemVerilog assertions. Experience with System Verilog verification environments including C/C++ DPI, UVM. Experience on any Scripting (Perl/Python/TCL). Excellent analytical and debug skills. Hands on usage of Low Power methodologies (UPF based preferably). Experience in UVM Acceleration.

Responsibilities

As a member of the Emulation Verification team, you will utilize Emulation for verification of large Wireless SoCs and be involved in bringing mixed signal models onto the Palladium platform. Your work will include porting the design onto the Palladium platform and executing the detailed Emulation test plan.