Engineer / Senior Engineer for Design-For-Test (DFT) at Infineon Technologies AG Australia

Hanoi, Ha Noi, Vietnam -

Full Time

Start Date

Immediate

Expiry Date

13 Mar, 26

Salary

0.0

Posted On

13 Dec, 25

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Design-For-Test, RTL Design, Verification, Automatic Test Pattern Generation, Test Coverage Analysis, Optimization, Scripting, Digital Design Flow, Scan Implementation, Post Silicon Analysis, Collaboration, Continuous Improvement, Automation, Fault Model, Hanoi

Industry

Semiconductor Manufacturing

Description

We are looking forward to working a bright and passionate talent specialized in Design-For-Test (DFT) at Hanoi, Vietnam. Your Role Key responsibilities in your new role Implementation and verification of DFT Logic in RTL and gate-level Automatic Test Pattern Generation for different fault model (StuckAt, Transition, IDDQ, etc.) Test coverage analysis and optimization Pattern re-simulation and gate level re-simulation Interface to test engineering for post silicon analysis Cooperation with design implementation, function verification team, and System-on-Chip and Design-For-Test concept engineers Automation of processes to increase efficiency Close collaboration with the DFT methodology experts and driving continuous improvement Your Profile Qualifications and skills to help you succeed Bachelor's Degree or above in Electrical Engineering, Computer Science, or similar domain 1-3 years of experience in Design-For-Test (DFT) and with specific flows and tools Hands-on experience with RTL design and verification Practical experience with scan implementation and Automatic Test Pattern Generation (ATPG) Good knowledge in overview of IC design Very good understanding of the digital design flow from specification until silicon debugging Good knowledge in scripting (e.g. Python, Perl, C-shell, TCL) for automation Fluent English language skills Contact: Nathan.Kim@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

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Responsibilities

The role involves the implementation and verification of DFT logic in RTL and gate-level, as well as automatic test pattern generation for various fault models. Additionally, it requires cooperation with design implementation and verification teams, and driving continuous improvement in DFT processes.