You Are

You understand that the real challenge in mixed-signal verification is not running simulations, it is building environments where analog and digital worlds talk to each other without breaking. You have spent time in the space between RTL and transistor-level netlists, where a single timing mismatch or convergence issue can derail a week of work, and you have learned how to catch those issues before they cascade.

You are comfortable reading a schematic, understanding such as ADC, AFE, PLL is supposed to do, and then building the test bench that proves it does it under every corner case that matters. Debugging does not intimidate you. You think of coverage and corner cases.

What You'll Be Doing

• Define and execute verification test plans for Ethernet and PCIe SERDES IP, tracking coverage metrics and ensuring completeness across functional, analog, and mixed-signal scenarios
• Build and maintain UVM-based SystemVerilog testbenches integrated with AMS co-simulation flows, combining RTL, behavioral models, and transistor-level netlists into unified verification platforms
• Verify SERDES subsystems including TX/RX datapaths, equalization algorithms, CDR loops, PLL locking behavior, and analog-digital interface interactions across process corners and operating conditions
• Debug simulation failures that span analog, digital, and mixed-signal domains using tools like HSPICE, XA, CustomSim, and VCS
• Perform design reliability checks including electromigration, IR drop analysis, and device-level stress evaluations to ensure robustness in production silicon
• Collaborate with mixed-signal designers, modeling engineers, and system architects across global Synopsys teams to align verification strategies with IP requirements and silicon timelines
• Develop Python, Perl, and shell-based automation to improve simulation throughput, regression efficiency, and debug workflows
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The Impact You Will Have

• Deliver verified IP that ships in high-volume production SoCs powering AI, automotive, cloud, and mobile applications
• Catch critical analog-digital interaction bugs before tapeout, directly preventing silicon respins and saving months of schedule and millions in cost
• Build reusable AMS co-simulation frameworks that accelerate verification cycles for future SERDES generations and reduce time-to-market
• Define verification methodologies that become the standard across Synopsys IPG teams, influencing how mixed-signal IP is verified company-wide
• Enable first-pass silicon success for SERDES products deployed in top-tier customer designs, strengthening Synopsys reputation and customer trust
• Mentor junior engineers and new graduates, raising the technical capability of the team and building institutional knowledge in AMS verification
• Drive improvements in coverage metrics, simulation performance, and debug efficiency that make the entire verification flow more predictable and scalable
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What You'll Need

• Bachelor's degree with 5 years’ relevant experience or Master's degree with minimum of 3 years of relevant experience (Electrical Engineering, Computer Engineering, or related field.
• Strong foundational understanding of analog and mixed-signal circuits including op-amps, bandgaps, PLLs, ADCs, TX/RX components, and high-speed interfaces
• Proficiency with System Verilog and UVM for digital and mixed-signal testbench development
• Experience with AMS simulation tools such as HSPICE, XA, CustomSim, or VCS AMS (for senior candidates, hands-on experience required; for new graduates, coursework or project exposure is sufficient)
• Solid scripting skills in Python, Perl, or UNIX shell for automation and productivity improvements
• For senior-level candidates, demonstrated experience in AMS co-simulation, SERDES verification, or behavioral modeling with a track record of owning verification flows and debugging complex analog-digital interactions
• Experience with design reliability analysis including EM/IR checks is a plus