Engineer, System Design Engineering at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

25 Jun, 26

Salary

0.0

Posted On

27 Mar, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Vip, Siemens Questa, Questa Advanced Simulator, Avery Vip, SystemVerilog, UVM, SoC Verification, Rtl Design, Waveform Analysis, Protocol Compliance, Regression Infrastructure, Verification Methodology, Problem-Solving, Cross-Team Collaboration

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Develop, integrate, and debug Verification IP (VIP) for industry‑standard protocols (e.g., PCIe or similar) Perform VIP‑based simulation using Siemens Questa / Questa Advanced Simulator Configure, customize, and maintain Avery VIPs (or equivalent) for block‑level, subsystem, and SoC‑level environments Build and maintain SystemVerilog / UVM testbenches Analyze functional coverage, assertions, and protocol compliance results Debug complex simulation failures using waveform analysis, assertions, and protocol checkers Collaborate with RTL designers to identify, root‑cause, and resolve functional issues Support regression infrastructure and improve simulation efficiency and stability Contribute to verification methodology, best practices, and reusable VIP components Qualifications Skill Sets: Strong hands‑on experience with VIP‑based verification Proven expertise in Siemens Questa (debug, coverage, assertions, performance tuning) Experience using Avery VIP (or equivalent VIPs such as Synopsys VCS VIP, Cadence VIP) Solid understanding of SystemVerilog and UVM Good knowledge of SoC verification flows Experience debugging protocol‑level issues in simulation Strong problem‑solving and cross‑team collaboration skills Requires BS/BA degree or equivalent in Electrical or Computer Engineering. The ideal individual must have proven ability to achieve results in a fast moving, dynamic and functionally-structured organizational environment. Self-motivated and self-directed, however, must have demonstrated ability to work well with people and in teams. Excellent communication (written and verbal) and interpersonal skills. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: Systems Design Engineering Work Location: Helios Office (IBH)--LOC_WDT_IBH

Responsibilities

The role involves developing, integrating, and debugging Verification IP (VIP) for industry-standard protocols like PCIe, utilizing tools such as Siemens Questa for simulation and configuration of Avery VIPs for various environment levels. Responsibilities also include building SystemVerilog/UVM testbenches, analyzing coverage, debugging failures, and collaborating with RTL designers to resolve functional issues.